NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 9 Reset Generation Module (MC_RGM)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 185
The F_LVD27 flag may still have the value 0 after a dip has occurred on the
2.7 V supply during a non-monotonic power-on sequence. The F_POR flag
will, however, still be set in this case as expected after each power-on
sequence.
In contrast to all other reset sources, the 1.2 V low-voltage detected (power
domain #0) event is captured on its deassertion. Therefore, the status bit
F_LVD12_PD0 is also asserted on the reset’s deassertion. In case an
alternate event is selected, the SAFE mode or interrupt request are similarly
asserted on the reset’s deassertion.
9.3.1.3 Functional Event Reset Disable Register (RGM_FERD)
This register provides dedicated bits to disable functional reset sources.When a functional reset source is
disabled, the associated functional event will trigger either a SAFE mode request or an interrupt request
(see
Section 9.3.1.5, Functional Event Alternate Request Register (RGM_FEAR) ). It can be accessed in
read/write in either supervisor mode or test mode. It can be accessed in read only in user mode. Each byte
can be written only once after power-on reset.
9.3.1.4 Destructive Event Reset Disable Register (RGM_DERD)
Address 0xC3FE_4004 Access: User read, Supervisor read, Test read
R
D_EXR
0 0 0 0 0 0
CHKST
OP
W
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-4. Functional Event Reset Disable Register (RGM_FERD)
Table 9-5. Functional Event Reset Disable Register (RGM_FERD) field descriptions
Field Description
D_EXR Disable External Reset
0 An external reset event triggers a reset sequence
1 An external reset event generates a SAFE mode request
Address 0xC3FE_4006 Access: Read
R 0 0 0 0 0 0 0 0 0 0 0
W
POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-5. Destructive Event Reset Disable Register (RGM_DERD)