NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 26 Deserial Serial Peripheral Interface (DSPI)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 625
26.6.4.2 CS to SCK delay (t
CSC
)
The CS _x to SCK _x delay is the length of time from assertion of the CS _x signal to the first SCK _x edge.
See Figure 26-16 for an illustration of the CS _x to SCK _x delay. The PCSSCK and CSSCK fields in the
DSPI x _CTAR n registers select the CS _x to SCK _x delay, and the relationship is expressed by the
following formula:
Table 26-26 shows an example of the computed CS to SCK _x delay.
26.6.4.3 After SCK delay (t
ASC
)
The after SCK _x delay is the length of time between the last edge of SCK _x and the negation of CS _x . See
Figure 26-16 and Figure 26-17 for illustrations of the after SCK _x delay. The PASC and ASC fields in the
DSPI x _CTAR n registers select the after SCK delay. The relationship between these variables is given in
the following formula:
Table 26-27 shows an example of the computed after SCK delay.
26.6.4.4 Delay after transfer (t
DT
)
The delay after transfer is the length of time between negation of the CS x signal for a frame and the
assertion of the CS x signal for the next frame. The PDT and DT fields in the DSPI x _CTAR n registers
select the delay after transfer.
See Figure 26-16 for an illustration of the delay after transfer.
The following formula expresses the PDT/DT/delay after transfer relationship:
Table 26-25. Baud rate computation example
f
SYS
PBR Prescaler value BR Scaler value DBR value Baud rate
64 MHz 0b00 2 0b0000 2 0 16 Mbit/s
20 MHz 0b00 2 0b0000 2 1 10 Mbit/s
Table 26-26. CS to SCK delay computation example
PCSSCK Prescaler value CSSCK Scaler value
f
SYS
CS to SCK delay
0b01 3 0b0100 32 64 MHz 1.5 µs
Table 26-27. After SCK delay computation example
PASC Prescaler value ASC Scaler value
f
SYS
After SCK delay
0b01 3 0b0100 32 64 MHz 1.5 µs
t
CSC
=
f
SYS
CSSCK

PCSSCK
1

t
ASC
=
f
SYS
ASC

PASC
1
