NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 26 Deserial Serial Peripheral Interface (DSPI)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 635
Figure 26-23. Continuous SCK timing diagram (CONT= 0)
If the CONT bit in the TX FIFO entry is set, CS remains asserted between the transfers when the CS signal
for the next transfer is the same as for the current transfer.
Figure 26-24 shows timing diagram for
continuous SCK format with continuous selection enabled.
Figure 26-24. Continuous SCK timing diagram (CONT=1)
26.6.7 Interrupt/DMA requests
The DSPI has five conditions that can generate interrupt requests only, and two conditions that can
generate interrupt or DMA requests.
Table 26-32 lists the seven conditions.
Table 26-32. Interrupt and DMA request conditions
Condition Flag Interrupt DMA
End of transfer queue has been reached (EOQ) EOQF X
TX FIFO is not full TFFF X X
SCK
(CPOL = 0)
CS
SCK
(CPOL = 1)
Master SOUT
t
DT
t
DT
= 1 SCK
Master SIN
SCK
(CPOL = 0)
CS
SCK
(CPOL = 1)
Master SOUT
Master SIN
Transfer 1 Transfer 2