NXP Semiconductors MPC5605BK, Reference Manual

Page: 139 / 964

Chapter 7 Clock Generation Module (MC_CGM)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 139
7.5.3 System Clock Select Status Register (CGM_SC_SS)
This register provides the current clock source selection for the following clocks:
• Undivided: system clock
• Divided by system clock divider 0: peripheral set 1 clock
• Divided by system clock divider 1: peripheral set 2 clock
• Divided by system clock divider 2: peripheral set 3 clock
See Figure 7-7 for details.
Table 7-4. Output Clock Division Select Register (CGM_OCDS_SC) field descriptions
Field Description
SELDIV Output Clock Division Select
00 output selected Output Clock without division
01 output selected Output Clock divided by 2
10 output selected Output Clock divided by 4
11 output selected Output Clock divided by 8
SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock.
0000 4-16 MHz ext. xtal osc.
0001 16 MHz int. RC osc.
0010 freq. mod. PLL
0011 system clock
0100 RTC clock
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
Address 0xC3FE_0378 Access: User read, Supervisor read, Test read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 SELSTAT 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 7-4. System Clock Select Status Register (CGM_SC_SS)