NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 7 Clock Generation Module (MC_CGM)
MPC5606BK Microcontroller Reference Manual, Rev. 2
142 Freescale Semiconductor
7.6 Functional Description
7.6.1 System Clock Generation
Figure 7-7 shows the block diagram of the system clock generation logic. The MC_ME provides the
system clock select and switch mask (see Chapter 8, Mode Entry Module (MC_ME) , for more details),
and the MC_RGM provides the safe clock request (see Chapter 9, Reset Generation Module (MC_RGM) ,
for more details). The safe clock request forces the selector to select the 16 MHz int. RC osc. as the system
clock and to ignore the system clock select.
Figure 7-7. MC_CGM System Clock Generation Overview
16 MHz int. RC osc.
4-16 MHz ext. xtal osc. 2
div. ext. xtal osc. 3
freq. mod. PLL 4
div. 16 MHz int. RC osc. 1
0
system clock
0
system clock is disabled if
ME_ <current mode> _MC.SYSCLK = 1111
CGM_SC_SS Register
MC_RGM safe clock request
MC_ME clock select
1
0
CGM_SC_DC0 Register
clock divider
peripheral set 1 clock
CGM_SC_DC1 Register
clock divider
peripheral set 2 clock
CGM_SC_DC2 Register
clock divider
peripheral set 3 clock