Table 42-1. Cycle definitions of decorated store: logical AND (continued)
Pipeline stage
Cycle
x
x+1
x+2
master_wt to slave_rd;
Capture address, attributes
BME AHB_dp
<previous>
Perform memory read; Form
(rdata & wdata) and capture
destination data in register
Perform write sending
registered data to memory
42.3.1.2 Decorated store logical OR (OR)
This command performs an atomic read-modify-write of the referenced memory location.
1. First, the location is read.
2. It is then modified by performing a logical OR operation using the write data operand
sourced for the system bus cycle.
3. Finally, the result of the OR operation is written back into the referenced memory
location.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit)
or word (32-bit). The core performs the required write data lane replication on byte and
halfword transfers.
ioorb
0
*
0
0
1
mem_addr
ioorh
0
0
0
1
mem_addr
ioorw
0
0
0
1
mem_addr
*
*
*
*
*
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Figure 42-4. Decorated address store: logical OR
See
,where addr[30:29] =10 for peripheral, addr[28:26] = 010 specifies the
OR operation, and mem_addr[19:0] specifies the address offset into the space based at
0x4000_0000 for peripherals. The "-" indicates an address bit "don't care".
The decorated OR write operation is defined in the following pseudo-code as:
ioor<sz>(accessAddress, wdata) // decorated store OR
tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read
tmp = tmp | wdata // modify
mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write
The cycle-by-cycle BME operations are detailed in the following table.
Chapter 42 Bit Manipulation Engine (BME)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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