no clock selected
(counter disable)
module clock
external clock
CMOD
synchronizer
CPWMS
PS
TOIE
TOF
MOD
Module counter
timer overflow
interrupt
Channel 0
MS0B:MS0A
ELS0B:ELS0A
input capture
mode logic
channel 0
input
C0V
CH0IE
CH0F
channel 0
interrupt
channel 0
output signal
output modes logic
prescaler
Channel N
MSNB:MSNA
ELSNB:ELSNA
input capture
mode logic
channel N
input
CNV
CHNIE
CHNF
channel N
interrupt
channel N
output signal
output modes logic
(generation of channel N outputs signals in
output compare, EPWM and CPWM modes)
(generation of channel 0 outputs signals in
output compare, EPWM and CPWM modes)
(1, 2, 4, 8, 16, 32, 64 or 128)
3
Figure 29-1. TPM block diagram
29.3 TPM Signal Descriptions
Table 29-4. TPM signal descriptions
Signal
Description
I/O
TPM_EXTCLK
External clock. TPM external clock can be selected to increment the TPM
counter on every rising edge synchronized to the counter clock.
I
TPM_CHn
TPM channel (n = 5 to 0). A TPM channel pin is configured as output when
configured in an output compare or PWM mode and the TPM counter is
enabled, otherwise the TPM channel pin is an input.
I/O
TPM Signal Descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
460
Freescale Semiconductor, Inc.
