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NXP Semiconductors MKL27Z128VFM4, Reference Manual

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The following figure is a simplified block diagram of the 4-channel DMA controller.

SAR0

DAR0
DSR0
BCR0

DCR0

Channel 0

SAR1

DAR1
DSR1
BCR1

DCR1

Channel 1

SAR2

DAR2
DSR2
BCR2

DCR2

Channel 2

SAR3

DAR3
DSR3
BCR3

DCR3

Channel 3

DREQ2

DACK3

DREQ0

DREQ1

Data Path

DREQ3

 

 

Addr + Attr

Interrupts

 

Phase Bus Signals

 

Current Master Attributes

 

Write Data Bus

 

Read Data Bus

 

System Bus Address

 

System Bus Size

 

 

SysBus Interface

MUX

SysBus Interface

 

Registered Addr

 

DACK2

DACK1

DACK0

Slave 

Peripheral Bus

Channel 

Requests

Channel 

Enables 

Channel 

Attributes

MUX 

Control

Arbitraton/ 

Control

Data Path 

Control

Figure 21-1. 4-Channel DMA Block Diagram

The terms peripheral request and DREQ refer to a DMA request from one of the on-chip
peripherals or package pins. The DMA provides hardware handshake signals: either a
DMA acknowledge (DACK) or a done indicator back to the peripheral.

21.1.2 Features

The DMA controller module features:

• Four independently programmable DMA controller channels

• Dual-address transfers via 32-bit master connection to the system bus

• Data transfers in 8-, 16-, or 32-bit blocks

• Continuous-mode or cycle-steal transfers from software or peripheral initiation

Introduction

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

308

Freescale Semiconductor, Inc.

Summary of Contents for MKL27Z128VFM4

Page 1: ...KL27 Sub Family Reference Manual Supports MKL27Z128VFM4 MKL27Z256VFM4 MKL27Z128VFT4 MKL27Z256VFT4 MKL27Z128VMP4 MKL27Z256VMP4 MKL27Z128VLH4 MKL27Z256VLH4 Document Number KL27P64M48SF6RM Rev 5 01 2016...

Page 2: ...KL27 Sub Family Reference Manual Rev 5 01 2016 2 Freescale Semiconductor Inc...

Page 3: ...nctional categories 40 2 2 1 ARM Cortex M0 core modules 41 2 2 2 System modules 41 2 2 3 Memories and memory interfaces 42 2 2 4 Clocks 42 2 2 5 Security and integrity modules 43 2 2 6 Analog modules...

Page 4: ...urces 53 Chapter 4 Memory Map 4 1 Introduction 55 4 2 Flash memory 55 4 2 1 Flash memory map 55 4 2 2 Flash security 56 4 2 3 Flash modes 56 4 2 4 Erase all flash contents 56 4 2 5 FTFA_FOPT register...

Page 5: ...ode clocking 70 5 6 Clock gating 71 5 7 Module clocks 71 5 7 1 PMC 1 kHz LPO clock 72 5 7 2 COP clocking 72 5 7 3 RTC clocking 73 5 7 4 RTC_CLKOUT and CLKOUT32K clocking 73 5 7 5 LPTMR clocking 74 5 7...

Page 6: ...oze 92 7 2 5 Clock gating 93 7 3 Power modes 93 7 4 Entering and exiting power modes 95 7 5 Module operation in low power modes 96 Chapter 8 Security 8 1 Introduction 101 8 1 1 Flash security 101 8 1...

Page 7: ...uts 115 10 5 Module Signal Description Tables 118 10 5 1 Core modules 118 10 5 2 System modules 118 10 5 3 Clock modules 119 10 5 4 Analog 119 10 5 5 Timer Modules 120 10 5 6 Communication interfaces...

Page 8: ...s 143 12 3 Memory map and register definition 144 12 3 1 System Options Register 1 SIM_SOPT1 145 12 3 2 SOPT1 Configuration Register SIM_SOPT1CFG 146 12 3 3 System Options Register 2 SIM_SOPT2 148 12...

Page 9: ...ROM Bootloader 13 1 Chip Specific Information 173 13 2 Introduction 173 13 3 Functional Description 175 13 3 1 Memory Maps 175 13 3 2 The Kinetis Bootloader Configuration Area BCA 176 13 3 3 Start up...

Page 10: ...ode Status register SMC_PMSTAT 230 14 5 Functional description 230 14 5 1 Power mode transitions 230 14 5 2 Power mode entry exit sequencing 233 14 5 3 Run modes 234 14 5 4 Wait modes 236 14 5 5 Stop...

Page 11: ...Control Register MCM_PLACR 251 16 2 4 Compute Operation Control Register MCM_CPO 254 Chapter 17 Crossbar Switch Lite AXBS Lite 17 1 Chip specific AXBS Lite information 257 17 1 1 Crossbar light switc...

Page 12: ...8 LLWU Flag 3 register LLWU_F3 277 18 4 9 LLWU Pin Filter 1 register LLWU_FILT1 279 18 4 10 LLWU Pin Filter 2 register LLWU_FILT2 280 18 5 Functional description 281 18 5 1 LLS mode 282 18 5 2 VLLS mo...

Page 13: ...20 4 Memory map register definition 297 20 4 1 Channel Configuration register DMAMUXx_CHCFGn 297 20 5 Functional description 298 20 5 1 DMA channels with periodic triggering capability 299 20 5 2 DMA...

Page 14: ...map and register descriptions 325 22 2 1 System Reset Status Register 0 RCM_SRS0 326 22 2 2 System Reset Status Register 1 RCM_SRS1 327 22 2 3 Reset Pin Filter Control register RCM_RPFC 328 22 2 4 Re...

Page 15: ...2 ADCx_SC2 351 23 4 7 Status and Control Register 3 ADCx_SC3 353 23 4 8 ADC Offset Correction Register ADCx_OFS 354 23 4 9 ADC Plus Side Gain Register ADCx_PG 355 23 4 10 ADC Minus Side Gain Register...

Page 16: ...23 5 3 Hardware trigger and channel selects 365 23 5 4 Conversion control 366 23 5 5 Automatic compare function 374 23 5 6 Calibration function 375 23 5 7 User defined offset function 377 23 5 8 Tempe...

Page 17: ...rol Register CMPx_SCR 400 24 3 5 DAC Control Register CMPx_DACCR 401 24 3 6 MUX Control Register CMPx_MUXCR 401 24 4 Functional description 402 24 4 1 CMP functional modes 403 24 4 2 Power modes 406 2...

Page 18: ...DACx_C2 418 25 5 Functional description 419 25 5 1 DAC data buffer operation 419 25 5 2 DMA operation 421 25 5 3 Resets 421 25 5 4 Low Power mode operation 421 Chapter 26 Voltage Reference VREFV1 26 1...

Page 19: ...G_S 437 27 2 4 MCG Status and Control Register MCG_SC 437 27 2 5 MCG Miscellaneous Control Register MCG_MC 438 27 3 Functional description 439 27 3 1 Clock mode switching 439 27 3 2 LIRC divider 1 440...

Page 20: ...4 28 12 Interrupts 454 Chapter 29 Timer PWM Module TPM 29 1 Chip specific TPM information 455 29 1 1 TPM instantiation information 455 29 1 2 Clock options 456 29 1 3 Trigger options 456 29 1 4 Global...

Page 21: ...3 Counter 475 29 5 4 Input Capture Mode 478 29 5 5 Output Compare Mode 479 29 5 6 Edge Aligned PWM EPWM Mode 480 29 5 7 Center Aligned PWM CPWM Mode 482 29 5 8 Registers Updated from Write Buffers 48...

Page 22: ...nal description 494 30 5 1 General operation 494 30 5 2 Interrupts 496 30 5 3 Chained timers 496 30 6 Initialization and application information 496 30 7 Example configuration for chained timers 497 3...

Page 23: ...31 5 6 LPTMR hardware trigger 511 31 5 7 LPTMR interrupt 511 Chapter 32 Real Time Clock RTC 32 1 Chip specific RTC information 513 32 1 1 RTC Instantiation Information 513 32 1 2 RTC_CLKOUT options 5...

Page 24: ...3 1 1 Universal Serial Bus USB FS Subsystem 527 33 1 2 USB Wakeup 527 33 1 3 USB Power Distribution 528 33 1 4 USB power management 530 33 2 Introduction 530 33 2 1 References 530 33 2 2 USB 531 33 2...

Page 25: ...er register Low USBx_FRMNUML 552 33 5 14 Frame Number register High USBx_FRMNUMH 552 33 5 15 BDT Page Register 2 USBx_BDTPAGE2 553 33 5 16 BDT Page Register 3 USBx_BDTPAGE3 553 33 5 17 Endpoint Contro...

Page 26: ...CK SPI Serial Clock 573 35 3 2 MOSI Master Data Out Slave Data In 573 35 3 3 MISO Master Data In Slave Data Out 573 35 3 4 SS Slave Select 573 35 4 Memory map register definition 574 35 4 1 SPI Status...

Page 27: ...Low power mode options 601 35 5 12 Reset 602 35 5 13 Interrupts 603 35 6 Initialization application information 605 35 6 1 Initialization sequence 605 35 6 2 Pseudo Code Example 606 Chapter 36 Inter I...

Page 28: ...CL Low Timeout Register Low I2Cx_SLTL 626 36 4 13 I2C Status register 2 I2Cx_S2 626 36 5 Functional description 627 36 5 1 I2C protocol 627 36 5 2 10 bit address 632 36 5 3 Address matching 634 36 5 4...

Page 29: ...itter functional description 666 37 4 3 Receiver functional description 668 37 4 4 Additional LPUART functions 673 37 4 5 Interrupts and status flags 675 Chapter 38 Universal Asynchronous Receiver Tra...

Page 30: ..._WN7816 701 38 4 18 UART 7816 Wait FD Register UARTx_WF7816 702 38 4 19 UART 7816 Error Threshold Register UARTx_ET7816 702 38 4 20 UART 7816 Transmit Length Register UARTx_TL7816 703 38 4 21 UART 781...

Page 31: ...40 38 9 4 Overrun NACK considerations 741 38 9 5 Match address registers 742 38 9 6 Clearing 7816 wait timer WT BWT CWT interrupts 742 38 9 7 Legacy and reverse compatibility considerations 742 Chapte...

Page 32: ...FTCFGn 759 39 3 13 Shifter Buffer N Register FLEXIO_SHIFTBUFn 760 39 3 14 Shifter Buffer N Bit Swapped Register FLEXIO_SHIFTBUFBISn 761 39 3 15 Shifter Buffer N Byte Swapped Register FLEXIO_SHIFTBUFBY...

Page 33: ...mit Configuration 3 Register I2Sx_TCR3 796 40 4 4 SAI Transmit Configuration 4 Register I2Sx_TCR4 797 40 4 5 SAI Transmit Configuration 5 Register I2Sx_TCR5 799 40 4 6 SAI Transmit Data Register I2Sx_...

Page 34: ...tion 822 41 2 1 Features 822 41 2 2 Modes of operation 822 41 2 3 GPIO signal descriptions 822 41 3 Memory map and register definition 824 41 3 1 Port Data Output Register GPIOx_PDOR 825 41 3 2 Port S...

Page 35: ...ro Trace Buffer MTB 43 1 Introduction 851 43 1 1 Overview 851 43 1 2 Features 854 43 1 3 Modes of operation 855 43 2 External signal description 855 43 3 Memory map and register definition 856 43 3 1...

Page 36: ...3 Register Descriptions 892 45 4 Functional Description 901 45 4 1 Flash Protection 901 45 4 2 Interrupts 902 45 4 3 Flash Operation in Low Power Modes 903 45 4 4 Functional Modes of Operation 903 45...

Page 37: ...es identify different numbering systems This suffix Identifies a b Binary number For example the binary equivalent of the number 5 is written 101b In some cases binary numbers are shown with the prefi...

Page 38: ...6 4 XAD 7 0 Numbers in brackets and separated by a colon represent either A subset of a register s named field For example REVNO 6 4 refers to bits 6 4 that are part of the COREREV field that occupies...

Page 39: ...to 48 MHz bus clock up to 24 MHz Memory option is up to 256 KB flash and 32 KB RAM Wide operating voltage ranges from 1 71 3 6 V with fully functional flash program erase read operations Multiple pac...

Page 40: ...ly and externally generated clocks MCG Lite with 48MIRC and 8M 2M IRC for systems and CPU clock sources Low power 1 kHz RC oscillator for RTC and COP watchdog System oscillator to provide clock source...

Page 41: ...is to detect asynchronous wake up events in stop modes and signal to clock control logic to resume system clocking After clock restart the NVIC observes the pending interrupt and performs the normal i...

Page 42: ...ly watchdog WDOG The WDOG monitors internal system operation and forces a reset in case of failure It can run from an independent 1 kHz low power oscillator 8 2 MHz internal oscillator or external cry...

Page 43: ...omparator Voltage reference VREF Supplies an accurate voltage output that is trimmable in 0 5 mV steps The VREF can be used in medical applications such as glucose meters to provide a reference voltag...

Page 44: ...al role USB controller that supports a full speed FS device The module complies with the USB 2 0 specification USB voltage regulator Up to 5 V regulator input typically provided by USB VBUS power with...

Page 45: ...0ALTTRGEN 0 Ch0 is A and Ch1 is B selecting this ADC trigger is for supporting A and B triggering In Stop and VLPS modes the second trigger must be set to 10 s after the first trigger LPTMR Hardware t...

Page 46: ...nput TPMx_CONF TRGSEL 4 bit field TPM1 Timebase to TPMx TPM Global timebase input TPMx_CONF GTBEEN PIT CHx TIF0 TIF1 to TPMx TPM Trigger input TPMx_CONF TRGSEL 4 bit field If PIT is triggering the TPM...

Page 47: ...Ln TRGSEL 4 bit field EXTRG_IN EXTRG_IN to FlexIO Trigger input FlexIO_TIMCTLn TRGSEL 4 bit field CMP0 CMP0_OUT to FlexIO Trigger input FlexIO_TIMCTLn TRGSEL 4 bit field 2 3 2 Analog reference options...

Page 48: ...UT Also when 1 2V VREF module is enabled adding supply to VREFH pad which is a dedicated 1 2 VREF_OUT pad from external is prohibited If ADC or DAC needs another reference voltage not equal to 1 2V at...

Page 49: ...profile processors 3 1 1 Buses interconnects and interfaces The ARM Cortex M0 core has two bus interfaces Single 32 bit AMBA 3 AHB Lite system interface that provides connections to peripherals and a...

Page 50: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R IRQ3 0 0 0 0 0 0 IRQ2 0 0 0 0 0 0 IRQ1 0 0 0 0 0 0 IRQ0 0 0 0 0 0 0 W 3 2 2 Non maskable interrupt The non maskable interrupt request to the NVIC is controlled...

Page 51: ...MA channel 0 transfer complete and error 0x0000_0044 17 1 0 DMA DMA channel 1 transfer complete and error 0x0000_0048 18 2 0 DMA DMA channel 2 transfer complete and error 0x0000_004C 19 3 0 DMA DMA ch...

Page 52: ...Pin detect Port A 0x0000_00BC 47 31 7 Port control module Pin detect Single interrupt vector for Port C Port D 1 Indicates the NVIC s interrupt source number 2 Indicates the NVIC s IPR register number...

Page 53: ...Available system resets RESET pin when LPO is its clock source Low voltage detect Power management controller functional in Stop mode Low voltage warning Power management controller functional in Sto...

Page 54: ...AWIC introduction KL27 Sub Family Reference Manual Rev 5 01 2016 54 Freescale Semiconductor Inc...

Page 55: ...ks consisting of 1 KB sectors The amounts of flash memory for the devices covered in this document are Table 4 1 KL27 Flash Memory Size Device Flash Memory KB Block 0 P Flash address range Block 1 P F...

Page 56: ...o be terminated with an error followed by the appropriate response in the requesting bus master 4 2 2 Flash security For information on how flash security is implemented on this device see Security 4...

Page 57: ...KB MKL27Z256VFM4 32 KB MKL27Z128VFT4 32 KB MKL27Z256VFT4 32 KB MKL27Z128VMP4 32 KB MKL27Z256VMP4 32 KB MKL27Z128VLH4 32 KB MKL27Z256VLH4 32 KB 4 3 2 SRAM ranges The on chip SRAM is split into two rang...

Page 58: ...00 SRAM_size 3 4 1 Figure 4 2 SRAM blocks memory map For example for a device containing 16 KB of SRAM the ranges are SRAM_L 0x1FFF_F000 0x1FFF_FFFF SRAM_U 0x2000_0000 0x2000_2FFF 4 3 3 SRAM retention...

Page 59: ...ed 0x4400_0000 0x5FFF_FFFF Bit Manipulation Engine BME access to AIPS Peripherals for slots 0 1273 Cortex M0 core 0x6000_0000 0xDFFF_FFFF Reserved 0xE000_0000 0xE00F_FFFF Private Peripherals Cortex M0...

Page 60: ...form peripheral devices The AIPS controller generates unique module enables for all 32 spaces A 384 KB region partitioned as 96 spaces each 4 KB in size and reserved for off platform modules The AIPS...

Page 61: ...ripheral register to verify the write 3 Continue with subsequent operations 4 7 2 Peripheral bridge AIPS Lite memory map Table 4 4 Peripheral bridge 0 slot assignments System 32 bit base address Slot...

Page 62: ...02_6000 38 0x4002_7000 39 0x4002_8000 40 0x4002_9000 41 0x4002_A000 42 0x4002_B000 43 0x4002_C000 44 0x4002_D000 45 0x4002_E000 46 0x4002_F000 47 I2S0 0x4003_0000 48 0x4003_1000 49 0x4003_2000 50 0x40...

Page 63: ...control 0x4004_A000 74 Port B multiplexing control 0x4004_B000 75 Port C multiplexing control 0x4004_C000 76 Port D multiplexing control 0x4004_D000 77 Port E multiplexing control 0x4004_E000 78 0x40...

Page 64: ...12 0x4007_1000 113 0x4007_2000 114 USB FS 0x4007_3000 115 Analog comparator CMP 6 bit digital to analog converter DAC 0x4007_4000 116 Voltage reference VREF 0x4007_5000 117 0x4007_6000 118 SPI0 0x4007...

Page 65: ...r have selectable clock input 5 2 Programming model The selection and multiplexing of system clock sources is controlled and programmed via the Clock Generation Module The setting of clock dividers an...

Page 66: ...le IRC48M will be controlled by IRC_TRIMs in MCG_Lite module Note3 FCRDIV support divider ratio 1 2 4 8 16 32 64 128 LIRC_DIV2 provides the futher divide down for MCGIRCLK Note4 OSC32KCLK is only avai...

Page 67: ...me modules that is chosen as OSC32KCLK or RTC_CLKIN or LPO LPO PMC 1 kHz output 5 4 1 Device clock summary The following table provides more information regarding the on chip clocks Table 5 1 Clock su...

Page 68: ...ERCLKEN cleared or Stop mode and OSC_CR EREFSTEN cleared or VLLS0 and oscillator not in external clock mode External reference 32kHz ERCLK32K 30 40 kHz 30 40 kHz System OSC or RTC_CLKIN or LPO System...

Page 69: ...via the SIM_CLKDIV1 register The following requirements must be met when configuring the clocks for this device The core platform and system clock are programmable from a divide by 1 through divide b...

Page 70: ...flash erased state defaults to fast clocking mode since these bits reside in flash which is logic 1 in the flash erased state To enable a lower power boot option program the appropriate bits in FTFA_...

Page 71: ...e clocks Module Bus interface clock Internal clocks I O interface clocks Core modules ARM Cortex M0 core Platform clock Core clock NVIC Platform clock DAP Platform clock SWD_CLK System modules DMA Sys...

Page 72: ...m Clock I2C0_SCL I2C1 System Clock I2C1_SCL LPUART0 LPUART1 Bus clock LPUART0 clock LPUART1 clock UART2 Bus clock FlexIO Bus clock FlexIO clock I2S Bus clock I2S master clock I2S_TX_BCLK I2S_RX_BCLK H...

Page 73: ...ure 5 3 RTC clock generation 5 7 4 RTC_CLKOUT and CLKOUT32K clocking When the RTC is enabled and the port control module selects the RTC_CLKOUT function the RTC_CLKOUT signal controlled from SIM_SOPT2...

Page 74: ...LKOUT32K Pad interface SIM_SOPT1 OSC32KSEL OSC32KCLK ERCLK32K 00 10 1 0 10 01 Other modules Other modules LPO 11 Figure 5 4 RTC_CLKOUT and CLKOUT32K generation 5 7 5 LPTMR clocking The prescaler and g...

Page 75: ...following figure NOTE The chosen clock must remain enabled if the TPMx is to continue operating in all required low power modes SIM_SOPT2 TPMSRC TPM clock MCGIRCLK OSCERCLK MCGPCLK 11 10 01 Figure 5...

Page 76: ...SRC MCGPCLK Figure 5 7 USB 48 MHz clock source 5 7 8 LPUART clocking The LPUART0 and LPUART1 have a selectable clock as shown in the following figure UART2 module operates from the bus clock NOTE The...

Page 77: ...ocking The FlexIO module has a selectable clock as shown in the following figure NOTE The chosen clock must remain enabled if the FlexIO is to continue operating in all required low power modes FlexIO...

Page 78: ...om the audio master clock or supplied externally The module also supports the option for synchronous operation between the receiver and transmitter The transmitter and receiver can independently selec...

Page 79: ...of the system reset sources has an associated bit in the System Reset Status SRS registers See the Reset Control Module for register details The MCU can exit and reset in functional mode where the CPU...

Page 80: ...Reads the start program counter PC from vector table offset 4 Link register LR is set to 0xFFFF_FFFF The on chip peripheral modules are disabled and the non analog I O pins are initially configured as...

Page 81: ...contents and control MCU system states during supply voltage variations The system consists of a power on reset POR circuit and an LVD circuit with a user selectable trip voltage The LVD system is alw...

Page 82: ...ntry to Stop mode if an error condition occurs The error can be caused by a failure of an external clock input to a module 6 2 2 6 Software reset SW The SYSRESETREQ field in the NVIC Application Inter...

Page 83: ...POR reset source only It resets the PMC The POR Only reset also causes all other reset types to occur 6 2 3 2 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources It rese...

Page 84: ...set types 6 2 4 RESET pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash init...

Page 85: ...on NMI input is disabled to platform when booting from ROM See FOPT section and Reset Control Module for more detail options The boot options can be overridden by using RCM_FM 2 1 and RCM_MR 2 1 which...

Page 86: ...ved through system resets and low power modes When RESET pin function is disabled it cannot be used as a source for low power mode wake up NOTE When the reset pin has been disabled and security has be...

Page 87: ...ocks that do not have clock gate control reset to disabled 3 The system reset on internal logic continues to be held but the Flash Controller is released from reset and begins initialization operation...

Page 88: ...sults in an NMI interrupt The processor executes an Exception Entry and reads the NMI interrupt handler address from vector table offset 8 The CPU begins execution at the NMI interrupt handler When FT...

Page 89: ...Partial Stop can be entered from either Run mode or VLP Run mode When configured for PSTOP2 only the core and system clocks are gated and the bus clock remains active The bus masters and bus slaves cl...

Page 90: ...ernal power switches enabling the clock generators in the MCG enabling the system and bus clocks but not the core clock and negating the stop mode signal to the bus masters and bus slaves The only dif...

Page 91: ...asynchronous DMA request 7 2 3 Compute Operation Compute Operation is an execution or compute only mode of operation that keeps the CPU enabled with full access to the SRAM and Flash read port but pla...

Page 92: ...MCM_CPO CPOACK indicates when entry has completed When exiting Compute Operation in Run mode MCM_CPO CPOACK negates immediately When exiting Compute Operation in VLP Run mode the exit is delayed to al...

Page 93: ...disables the clock to the corresponding module Prior to initializing a module set the corresponding bit in the SCGCx register to enable the clock Before turning off the clock make sure to disable the...

Page 94: ...l 4 MHz source for the core with the nominal bus and flash clock required to be 1 MHz Alternatively EXT clock mode can be used with an external clock or the crystal oscillator providing the clock sour...

Page 95: ...e powered off The 32 byte system register file remains powered for customer critical data LPO disabled optional POR brown out detection Sleep Deep Wake up Reset2 1 Resumes Normal Run mode operation by...

Page 96: ...states and associated memories are retained powered Memory is powered to retain contents low power Memory is powered to retain contents in a lower power state OFF Modules are powered off module is in...

Page 97: ...Hz max OFF OFF OFF OFF System clock 4 MHz max OFF in CPO 4 MHz max OFF OFF OFF OFF Bus clock 1 MHz max OFF in CPO 1 MHz max OFF 24 MHz max in PSTOP2 from RUN 1 MHz max in PSTOP2 from VLPR OFF OFF OFF...

Page 98: ...c address match wakeup static address match wakeup static OFF I2C1 100 kbit s static address match wakeup in CPO 100 kbit s static address match wakeup static address match wakeup static OFF I2S FF As...

Page 99: ...the external pins available for this chip do not require the associated peripheral function to be enabled It only requires the function controlling the pin GPIO or peripheral to be configured as an i...

Page 100: ...Module operation in low power modes KL27 Sub Family Reference Manual Rev 5 01 2016 100 Freescale Semiconductor Inc...

Page 101: ...al accesses debug CPU accesses to the flash are not affected by the status of FTFA_FSEC In the unsecured state all flash commands are available on the programming interfaces either from the debug port...

Page 102: ...ger can write to the Flash Mass Erase in Progress field of the MDM AP Control register to trigger a mass erase Erase All Blocks command A mass erase via the debugger is allowed even when some memory l...

Page 103: ...is supported Serial Wire Debug SWD 9 2 Debug port pin descriptions The debug port pins default after POR to their SWD functionality Table 9 1 Serial wire debug pin description Pin name Type Descriptio...

Page 104: ...witch thus remaining less intrusive during a debug session It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessibl...

Page 105: ...L STAT AP Select SELECT Read Buffer RDBUFF DP Registers 0x00 0x04 0x08 0x0C Data 31 0 A 3 2 RnW DPACC Data 31 0 A 3 2 RnW APACC Debug Port DP Generic See the ARM Debug Interface v5p1 Supplement Figure...

Page 106: ...debugger time to re initialize debug IP before the debug session continues The Mode Controller captures this bit logic on entry to VLLSx modes Upon exit from VLLSx modes the Mode Controller will hold...

Page 107: ...e is disabled 1 Mass erase is enabled 6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled 0 Disabled 1 Enabled 7 LP Enabled Decode of SMC_PMCTRL STOPM field to indica...

Page 108: ...VLLSx Status Acknowledge bit in MDM AP Control register 11 15 Reserved for future use Always read 0 16 Core Halted Indicates the core has entered Debug Halt mode 17 Core SLEEPDEEP Indicates the core...

Page 109: ...odes In low power modes in which the debug modules are kept static or powered off the debugger cannot gather any debug data for the duration of the low power mode In the case that the debugger is held...

Page 110: ...ger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation 9 7 Debug and security When flash security is enabled the debug port capabilities are limite...

Page 111: ...ltiplexing integration Information found here summarizes how the module is integrated into the device For a comprehensive description of the module itself see the module s dedicated chapter Register a...

Page 112: ...age pin Do not program the same function to more than one pin 2 To ensure the best signal timing for a given peripheral s interface choose the pins in closest proximity to each other 10 3 KL27 Signal...

Page 113: ...0_SE12 ADC0_SE12 PTB2 I2C0_SCL TPM2_CH0 30 E8 38 PTB3 ADC0_SE13 ADC0_SE13 PTB3 I2C0_SDA TPM2_CH1 31 E6 39 PTB16 DISABLED PTB16 SPI1_MOSI LPUART0_ RX TPM_CLKIN0 SPI1_MISO 32 D7 40 PTB17 DISABLED PTB17...

Page 114: ...9 XTAL0 XTAL0 PTA19 LPUART1_ TX TPM_CLKIN1 LPTMR0_ ALT1 19 26 F8 34 PTA20 RESET_b PTA20 RESET_b 20 27 F7 35 PTB0 LLWU_P5 ADC0_SE8 ADC0_SE8 PTB0 LLWU_P5 I2C0_SCL TPM1_CH0 21 28 F6 36 PTB1 ADC0_SE9 ADC0...

Page 115: ...outs Figure below shows the 32 QFN pinouts 32 31 30 29 28 27 26 25 PTD7 PTD6 LLWU_P15 PTD5 PTD4 LLWU_P14 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC4 LLWU_P8 PTA2 PTA1 PTA0 PTE30 12 11 10 9 VSS VDD PTA4 PTA3...

Page 116: ..._P9 PTC4 LLWU_P8 36 35 34 33 PTC3 LLWU_P7 PTC2 PTC1 LLWU_P6 RTC_CLKIN PTC0 32 31 30 29 28 27 26 25 PTB17 PTB16 PTB3 PTB2 PTB1 PTB0 LLWU_P5 PTA20 PTA19 PTA3 PTA2 PTA1 PTA0 24 23 22 21 20 19 18 17 PTE25...

Page 117: ...61 PTD7 PTD6 LLWU_P15 PTD5 PTD4 LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6 LLWU_P10 PTC5 LLWU_P9 PTC4 LLWU_P8 VDD VSS PTC3 LLWU_P7 PTC2 PTC1 LLWU_P6 RTC_CLKIN PTC0 PTB19 PTB18 PTB17...

Page 118: ...TB3 F PTA20 G PTA19 8 H PTA18 Figure 10 5 64 MAPBGA Pinout diagram 10 5 Module Signal Description Tables 10 5 1 Core modules Table 10 2 SWD signal descriptions Chip signal name Module signal name Desc...

Page 119: ...ptions Chip signal name Module signal name Description I O EXTAL0 EXTAL External clock Oscillator input I XTAL0 XTAL Oscillator output O 10 5 4 Analog This table presents the signal descriptions of th...

Page 120: ...DAC0_OUT DAC output O Table 10 9 VREF signal descriptions Chip signal name Module signal name Description I O VREF_OUT VREF_OUT Internally generated voltage reference output O 10 5 5 Timer Modules Ta...

Page 121: ...0 A TPM channel pin is configured as output when configured in an output compare or PWM mode and the TPM counter is enabled otherwise the TPM channel pin is an input I O Table 10 13 LPTMR0 signal des...

Page 122: ...SPI1_MISO MISO Master Data In Slave Data Out I O SPI1_MOSI MOSI Master Data Out Slave Data In I O SPI1_SCLK SPSCK SPI Serial Clock I O SPI1_PCS0 SS Slave Select I O Table 10 19 I2C0 signal descriptio...

Page 123: ...n output when internally generated I O I2S0_RX_FS SAI_RX_SYNC Receive Frame Sync The frame sync is an input sampled synchronously by the bit clock when externally generated and an output generated syn...

Page 124: ...0 26 GPIO Signal Descriptions Chip signal name Module signal name Description I O PTA 20 0 PORTA20 PORTA0 General purpose input output I O PTB 19 0 PORTB19 PORTB0 General purpose input output I O PTD...

Page 125: ...030 4004_A03C PORTB_PCR12 PORTB_PCR13 PORTB_PCR14 and PORTB_PCR15 4004_A060 4004_A07C PORTB_PCR24 PORTB_PCR25 PORTB_PCR26 PORTB_PCR27 PORTB_PCR28 PORTB_PCR29 PORTB_PCR30 and PORTB_PCR31 4004_B038 PORT...

Page 126: ...ed Disabled Slew rate enable control Yes Yes Yes Yes Yes Slew rate enable at reset PTA3 PTA14 PTA15 PTA16 PTA17 Fast Slew Others Slow Slew PTB10 PTB11 PTB16 PTB17 Fast Slew Others Slow Slew PTC3 PTC4...

Page 127: ...w The Port Control and Interrupt PORT module provides support for port control and external interrupt functions Most functions can be configured independently for each pin in the 32 bit port and affec...

Page 128: ...d GPIO and up to chip specific digital functions Pad configuration fields are functional in all digital pin muxing modes 11 4 2 Modes of operation 11 4 2 1 Run mode In Run mode the PORT operates norma...

Page 129: ...asynchronously to the system clock Negation may occur at any time and can assert asynchronously to the system clock 11 7 Memory map and register definition Any read or write access to the PORT memory...

Page 130: ...tion 11 7 1 135 4004_9050 Pin Control Register n PORTA_PCR20 32 R W See section 11 7 1 135 4004_9054 Pin Control Register n PORTA_PCR21 32 R W See section 11 7 1 135 4004_9058 Pin Control Register n P...

Page 131: ...11 7 1 135 4004_A050 Pin Control Register n PORTB_PCR20 32 R W See section 11 7 1 135 4004_A054 Pin Control Register n PORTB_PCR21 32 R W See section 11 7 1 135 4004_A058 Pin Control Register n PORTB...

Page 132: ...tion 11 7 1 135 4004_B050 Pin Control Register n PORTC_PCR20 32 R W See section 11 7 1 135 4004_B054 Pin Control Register n PORTC_PCR21 32 R W See section 11 7 1 135 4004_B058 Pin Control Register n P...

Page 133: ...11 7 1 135 4004_C050 Pin Control Register n PORTD_PCR20 32 R W See section 11 7 1 135 4004_C054 Pin Control Register n PORTD_PCR21 32 R W See section 11 7 1 135 4004_C058 Pin Control Register n PORTD...

Page 134: ...048 Pin Control Register n PORTE_PCR18 32 R W See section 11 7 1 135 4004_D04C Pin Control Register n PORTE_PCR19 32 R W See section 11 7 1 135 4004_D050 Pin Control Register n PORTE_PCR20 32 R W See...

Page 135: ...field Varies by port See the Signal Multiplexing and Signal Descriptions chapter for reset values per port PFE field Varies by port See Signal Multiplexing and Signal Descriptions chapter for reset v...

Page 136: ...ISF flag and DMA request on either edge 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 ISF flag and Interrupt when logic 0 1001 ISF flag and Interrupt on rising edge 1010 ISF flag and I...

Page 137: ...pins that do not support a configurable slew rate Slew rate configuration is valid in all digital pin muxing modes 0 Fast slew rate is configured on the corresponding pin if the pin is configured as a...

Page 138: ...sters bits 15 0 that are selected by GPWE 11 7 3 Global Pin Control High Register PORTx_GPCHR Only 32 bit writes are supported to this register Address Base address 84h offset Bit 31 30 29 28 27 26 25...

Page 139: ...corresponding flag will be cleared automatically at the completion of the requested DMA transfer Otherwise the flag remains set until a logic 1 is written to the flag If the pin is configured for a l...

Page 140: ...s not connected or an output pin that has tri stated output buffer is disabled Enabling the internal pull resistor or implementing an external pull resistor will ensure a pin does not float when its i...

Page 141: ...that asserts when the interrupt status flag is set for any enabled interrupt for that port The interrupt negates after the interrupt status flags for all enabled interrupts have been cleared by writi...

Page 142: ...Functional description KL27 Sub Family Reference Manual Rev 5 01 2016 142 Freescale Semiconductor Inc...

Page 143: ...l and chip configuration registers 12 2 1 Features System clocking configuration System clock divide values Architectural clock gating control ERCLK32K clock selection USB clock selection LPUART and T...

Page 144: ...ice Identification Register SIM_SDID 32 R See section 12 3 7 154 4004_8034 System Clock Gating Control Register 4 SIM_SCGC4 32 R W F000_0030h 12 3 8 156 4004_8038 System Clock Gating Control Register...

Page 145: ...in standby mode during Stop VLPS LLS and VLLS modes Controls whether the USB voltage regulator is placed in standby mode during Stop VLPS LLS and VLLS modes 0 USB voltage regulator not in standby dur...

Page 146: ...LVD 00 ERCLK32K is not output 01 ERCLK32K is output on PTE0 10 ERCLK32K is output on PTE26 11 Reserved 15 6 Reserved This field is reserved This read only field is reserved and always has the value 0...

Page 147: ...able Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written This register bit clears after a write to USBVSTBY 0 SOPT1 USBVSTB cannot be written 1 SOPT1 USBVSTB can be written 24 URW...

Page 148: ...0 0 0 0 SIM_SOPT2 field descriptions Field Description 31 30 Reserved This field is reserved This read only field is reserved and always has the value 0 29 28 LPUART1SRC LPUART1 Clock Source Select S...

Page 149: ...d and always has the value 0 15 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 5 CLKOUTSEL CLKOUT select Selects the clock to output on the CLKOUT pin...

Page 150: ...ternal clock driven by TPM_CLKIN0 pin 1 TPM2 external clock driven by TPM_CLKIN1 pin 25 TPM1CLKSEL TPM1 External Clock Pin Select Selects the external pin used to drive the clock to the TPM1 module NO...

Page 151: ...in input capture mode clear this field 00 TPM1_CH0 signal 01 CMP0 output 10 Reserved 11 USB start of frame pulse Reserved This field is reserved This read only field is reserved and always has the va...

Page 152: ...e Select Selects the source for the LPUART1 receive data 0 LPUART1_RX pin 1 CMP0 output 5 4 LPUART1TXSRC LPUART1 Transmit Data Source Select Selects the source for the LPUART1 transmit data 00 LPUART1...

Page 153: ...B to initiate an ADC acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB Register 1 ADC ADHWT trigger comes from a peripheral event selected by ADC0TRGSEL bits ADC0PRETRGSEL b...

Page 154: ...rved 12 3 7 System Device Identification Register SIM_SDID Address 4004_7000h base 1024h offset 4004_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R F...

Page 155: ...e Specifies the size of the System SRAM 0101 16 KB 0110 32 KB 15 12 REVID Device Revision Number Specifies the silicon implementation number for the device 11 4 Reserved This field is reserved This re...

Page 156: ...reserved This read only field is reserved and always has the value 0 23 SPI1 SPI1 Clock Gate Control Controls the clock gate to the SPI1 module 0 Clock disabled 1 Clock enabled 22 SPI0 SPI0 Clock Gate...

Page 157: ...10 Reserved This field is reserved This read only field is reserved and always has the value 0 9 Reserved This field is reserved This read only field is reserved and always has the value 0 8 Reserved...

Page 158: ...is reserved This read only field is reserved and always has the value 0 21 LPUART1 LPUART1 Clock Gate Control This bit controls the clock gate to the LPUART1 module 0 Clock disabled 1 Clock enabled 20...

Page 159: ...enabled 8 7 Reserved This field is reserved This read only field is reserved and always has the value 1 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5...

Page 160: ...ed 30 Reserved This field is reserved This read only field is reserved and always has the value 0 29 RTC RTC Access Control Controls software access and interrupts to the RTC module 0 Access and inter...

Page 161: ...ue 0 17 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 I2S I2S Clock Gate Control This bit controls the clock gate to the I2S module 0 Clock disabled...

Page 162: ...ved This read only field is reserved and always has the value 0 12 3 12 System Clock Divider Register 1 SIM_CLKDIV1 NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode NOTE...

Page 163: ...e by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 1111 Divide by 16 27 19 Reserved This field is reserved This read only field is reserved and always has the value 0 18 1...

Page 164: ...27 24 PFSIZE Program Flash Size Specifies the amount of program flash memory available on the device Undefined values are reserved 0000 8 KB of program flash memory 1 KB protection region 0001 16 KB o...

Page 165: ...Flash Disable Flash accesses are disabled and generate a bus error and the flash memory is placed in a low power state This field should not be changed during VLP modes Relocate the interrupt vectors...

Page 166: ...block flash block 1 For example if MAXADDR0 MAXADDR1 0x10 the first invalid address of flash block 1 is 0x2_0000 0x2_0000 This would be the MAXADDR1 value for a device with 256 KB program flash memory...

Page 167: ...ation Unique identification for the device 12 3 17 Unique Identification Register Low SIM_UIDL Address 4004_7000h base 1060h offset 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 168: ...d is reserved and always has the value 0 7 6 COPCLKSEL COP Clock Select This write once field selects the clock source of the COP watchdog 00 LPO clock 1 kHz 01 MCGIRCLK 10 OSCERCLK 11 Bus clock 5 COP...

Page 169: ...through the timeout period and will generate a system reset if the COP is serviced outside of that time 0 Normal mode 1 Windowed mode 12 3 19 Service COP SIM_SRVCOP This is write only register any re...

Page 170: ...n 0x55 or 0xAA is written to the SRVCOP register the microcontroller immediately resets SIM_COPC COPCLKS and SIM_COPCTRL COPCLKSEL select the timeout duration and clock source used for the COP timer T...

Page 171: ...clear the COP timer must occur in the last 25 of the selected timeout period A premature write immediately resets the chip When the short timeout COPCLKS 0 is selected windowed COP operation is not av...

Page 172: ...top mode The COP counter can also be configured to continue incrementing during Debug mode or Stop including VLPS mode if either COPDBGEN or COPSTPEN are set respectively When the selected clock is th...

Page 173: ...Table 13 1 Kinetis Bootloader Peripheral Pinmux Port Signal PTA2 LPUART0_TX PTA1 LPUART0_RX PTB0 I2C0_SCL PTB1 I2C0_SDA PTC4 SPI0_SS_b PTC7 SPI0_MISO PTC6 SPI0_MOSI PTC5 SPI0_SCK USB0_DP USB0_DP USB0...

Page 174: ...s optional configuration parameters from a fixed area on flash called the bootloader configuration area BCA These parameters can be modified by the write memory command or by downloaded flash image BC...

Page 175: ...t the current value of a property Supported Reset Reset the chip Supported SetProperty Attempt to modify a writable property Supported FlashEraseAllUnsecure Erase the entire flash array including prot...

Page 176: ...f peripherals to enable bit 0 LPUART bit 1 I2C bit 2 SPI bit 4 USB Kinetis bootloader will enable the peripheral if corresponding bit is set to 1 0x11 1 i2cSlaveAddress If not 0xFF used as the 7 bit I...

Page 177: ...er assumes that the flash is not initialized and uses a predefined default configuration The tag value is treated as a character string so bytes 0 3 must be set as shown in the table Table 13 4 tag Co...

Page 178: ...that any exceptions will be handled by the ROM After the Kinetis Bootloader has started the following procedure starts bootloader operations 1 The RCM_MR FORCEROM bits are set so that the device will...

Page 179: ...2Cn entered interrupt state Ping packet received on LPUARTn Shutdown unused Peripherals Jump to user application Enter bootloader state machine No Yes No No No Yes No Yes Yes Yes Has Has Was a Use the...

Page 180: ...ck divider is increased until the bus clock frequency is at or below the maximum Note that the maximum baud rate of serial peripherals is related to the core and bus clock frequencies To achieve the d...

Page 181: ...sactions such as commands with no data phase and commands with incoming or outgoing data phase The next section describes various packet types used in a transaction Each command sent from the host is...

Page 182: ...Response ACK Figure 13 3 Command with No Data Phase 13 3 6 2 Command with incoming data phase The protocol for a command with an incoming data phase contains Command packet from host Generic response...

Page 183: ...ackets while it the host is waiting for the response to a command If the Generic Response packet prior to the start of the data phase does not have a status of kStatus_Success then the data phase is a...

Page 184: ...tire operation 13 3 6 3 Command with outgoing data phase The protocol for a command with an outgoing data phase contains Command packet from host ReadMemory Response command packet to host kCommandFla...

Page 185: ...e data phase is really considered part of the response command The host may not send any further packets while it the host is waiting for the response to a command If the ReadMemory Response command p...

Page 186: ...is packetized NOTE The term target refers to the Kinetis Bootloader device There are 6 types of packets used in the device Ping packet Ping Response packet Framing packet Command packet Data packet Re...

Page 187: ...coming Ping packet to determine the baud rate before replying with the Ping Response packet Once the Ping Response packet is received by the host the connection is established and the host starts send...

Page 188: ...RC16 algorithm after this table 5 crc16_high 6 n Command or Data packet payload A special framing packet that contains only a start byte and a packet type is used for synchronization between the host...

Page 189: ...ntains the framing protocol version number and options CRC16 algorithm uint16_t crc16_update const uint8_t src uint32_t lengthInBytes uint32_t crc 0 uint32_t j for j 0 j lengthInBytes j uint32_t i uin...

Page 190: ...llowed by 32 bit parameters up to the value of the ParameterCount field specified in the header Because a command packet is 32 bytes long only 7 parameters can fit into the command packet Command pack...

Page 191: ...ParameterCount The number of parameters included in the command packet Parameters The parameters are word length 32 bits With the default maximum packet size of 32 bytes a command packet can contain...

Page 192: ...d by the target Kinetis Bootloader If a command succeeds then a kStatus_Success code is returned Table 13 40 Kinetis Bootloader Status Error Codes lists the status codes returned to the host by the Ki...

Page 193: ...supported by the Kinetis Bootloader in KLx3 ROM see Table 13 2 Commands supported For a list of status codes returned by the Kinetis Bootloader in KLx3 ROM see Table 13 40 Kinetis Bootloader Status E...

Page 194: ...e Reset command will result in bootloader resetting the chip The Reset command requires no parameters Process command Host Target Reset 0x5a a4 04 00 6f 46 0b 00 00 00 GenericResponse 0x5a a4 0c 00 f8...

Page 195: ...packet The target returns a GetPropertyResponse packet with the property values for the property identified with the tag in the GetProperty command Properties are the defined units of data that can b...

Page 196: ...00001 CurrentVersion The GetProperty command has no data phase Response In response to a GetProperty command the target will send a GetPropertyResponse packet with the response tag set to 0xA7 The par...

Page 197: ...inetis Bootloader ROM However the SetProperty command can only change the value of properties that are writable see Table 13 36 Properties used by Get SetProperty Commands If you try to set a value fo...

Page 198: ...cketType_Command length 0x0C 0x00 crc16 0x67 0x8D Command packet commandTag 0x0C SetProperty with property tag 10 flags 0x00 reserved 0x00 parameterCount 0x02 propertyTag 0x0000000A VerifyWrites prope...

Page 199: ...the commandTag field of the command packet The FlashEraseAll command requires no parameters Process command Host Target FlashEraseAll 0x5a a4 04 00c4 2e 01 00 00 00 0x5a a4 0c 00 53 63 a0 00 04 02 00...

Page 200: ...return kStatus_FlashAlignmentError 0x101 If the region specified does not fit in the flash memory space the FlashEraseRegion command will fail and return kStatus_FlashAddressError 0x102 If any part o...

Page 201: ...tatus_Success 0x0 kStatus_MemoryRangeInvalid 0x10200 kStatus_FlashAlignmentError 0x101 kStatus_FlashAddressError 0x102 kStatus_FlashAccessError 0x103 kStatus_FlashProtectionViolation 0x104 kStatus_Fla...

Page 202: ...0x00 The FlashEraseAllUnsecure command has no data phase Response The target Kinetis Bootloader will return a GenericResponse packet with status code either set to kStatus_Success for successful exec...

Page 203: ...shSecurityDisable Parameter Value Framing packet start byte 0x5A packetType 0xA4 kFramingPacketType_Command length 0x0C 0x00 crc16 0x43 0x7B Command packet commandTag 0x06 FlashSecurityDisable flags 0...

Page 204: ...dress to be 4 byte aligned 1 0 00 The byte count will be rounded up to a multiple of 4 and the trailing bytes will be filled with the flash erase pattern 0xff If the VerifyWrites property is set to tr...

Page 205: ...00 04 00 00 00 ACK 0x5a a1 0x5a a4 0c 00 a0 0e 04 01 00 02 00 04 00 20 40 00 00 00 Figure 13 14 Protocol Sequence for WriteMemory Command Table 13 34 WriteMemory Command Packet Format Example WriteMe...

Page 206: ...3 8 10 Read memory command The ReadMemory command returns the contents of memory at the given address for a specified number of bytes This command can read any region of memory accessible by the CPU a...

Page 207: ...data 0x5a a5 length 16 CRC 16 32 bytes data ACK 0x5a a1 ACK 0x5a a1 ACK 0x5a a1 ACK 0x5a a1 ACK 0x5a a1 0x5a a4 0c 00 0e 23 a0 00 00 02 00 00 00 00 03 00 00 00 Figure 13 15 Command sequence for read m...

Page 208: ...ceptions I2C and SPI are restored by writing the control registers to reset values LPUART is not restored Peripheral pin mux is not reset to default see the pin mux table Kinetis Bootloader Peripheral...

Page 209: ...the transfer Customizing an I2C slave address is also supported This feature is enabled if the Bootloader Configuration Area BCA shown in Table 13 3 is enabled tag field is filled with kcfg and the i...

Page 210: ...End Report Error No No Read 1 byte from target 0x5A received packet Read leftover bytes of ping response 0x7A received Read 1 byte from target Figure 13 16 Host reads ping response from target via I2...

Page 211: ...13 3 The typical supported baud rate is 400 kbps with the factory settings The actual baud rate is lower or higher than 400 kbps depending on the actual value of the clockFlags and clockDivider field...

Page 212: ...ets to identify real data and not dummy 0x00 bytes which do not have framing packets The following flowcharts demonstrate how the host reads a ping response an ACK and a command response from target v...

Page 213: ...payload data from target No Set payload length to maximum supported length No No maximum Report a timeout error End Yes End No 2 bytes 0x5A received 0xA4 received Reached retries Send 0x00 to shift ou...

Page 214: ...ngs Manufacturer 1 Freescale Semiconductor Inc Product 2 Kinetis Bootloader You can customize the USB VID PID Strings with the Bootloader Configuration Area BCA of the flash See Table 13 3 For example...

Page 215: ...TR_3 is used for the serial number string By default the 3 strings are defined as below USB_STR_1 sizeof USB_STR_1 USB_STRING_DESCRIPTOR F 0 r 0 e 0 e 0 s 0 c 0 a 0 l 0 e 0 0 S 0 e 0 m 0 i 0 c 0 o 0 n...

Page 216: ...a pipe where the firmware can NAK send requests from the USB host 13 4 3 4 HID reports There are 4 HID reports defined and used by the bootloader USB HID peripheral The report ID determines the direct...

Page 217: ...MSB 3 Packet 0 4 Packet 1 5 Packet 2 N 3 1 Packet N 1 This data includes the Report ID which is required if more than one report is defined in the HID report descriptor The actual data sent and receiv...

Page 218: ...active peripheral interface ReservedRegions No 0Ch 16 List of memory regions reserved by the bootloader Returned as value pairs start address of region end address of region If HasDataPhase flag is no...

Page 219: ...C USB HID Reserved SPI Slave I2C Slave LPUART If the peripheral is available then the corresponding bit will be set in the property value All reserved bits must be set to 0 13 5 1 3 AvailableCommands...

Page 220: ...ot used kStatus_FlashAlignmentError 101 Address or length does not meet required alignment kStatus_FlashAddressError 102 Address or length is outside addressable memory kStatus_FlashAccessError 103 Th...

Page 221: ...section found in the SB file kStatusRomLdrDataUnderrun 10109 The SB state machine is waiting for more data kStatusRomLdrJumpReturned 10110 The function that was jumped to by the SB file has returned...

Page 222: ...ck Workaround Send ping packet bytes continuously without delay Limit highest UART clock frequency to 38400 at default clock 8 MHz To improve UART throughput configure the core clock to higher frequen...

Page 223: ...the power clocks and memories of the system to achieve the power consumption and functionality of that mode This chapter describes all the available low power modes the sequence followed to enter exi...

Page 224: ...R mode when limited frequency is sufficient for the application From VLPR mode a corresponding wait VLPW and stop VLPS mode can be entered Depending on the needs of the user application a variety of s...

Page 225: ...ed in a low leakage mode by powering down the internal logic and all system RAM I O states are held Internal logic states are not retained VLLS0 The core clock is gated off System clocks to other mast...

Page 226: ...ttempt to enter VLPR mode using PMCTRL RUNM is blocked and PMCTRL RUNM remains 00b indicating the MCU is still in Normal Run mode NOTE This register is reset on Chip Reset not VLLS and by reset types...

Page 227: ...ery low leakage stop mode VLLSx 0 Any VLLSx mode is not allowed 1 Any VLLSx mode is allowed 0 Reserved This field is reserved This read only field is reserved and always has the value 0 14 4 2 Power M...

Page 228: ...The previous stop mode entry was successful 1 The previous stop mode entry was aborted STOPM Stop Mode Control When written controls entry into the selected stop mode when Sleep Now or Sleep On Exit...

Page 229: ...s running on bus clock to remain fully functional In PSTOP1 both system and bus clocks are gated 00 STOP Normal Stop mode 01 PSTOP1 Partial Stop with both system and bus clocks disabled 10 PSTOP2 Part...

Page 230: ...atus NOTE When debug is enabled the PMSTAT will not update to STOP or VLPS NOTE When a PSTOP mode is enabled the PMSTAT will not update to STOP or VLPS 0000_0001 Current power mode is RUN 0000_0010 Cu...

Page 231: ...Power mode transition triggers Transition From To Trigger conditions 1 RUN WAIT Sleep now or sleep on exit modes entered with SLEEPDEEP clear controlled in System Control Register in ARM core See not...

Page 232: ...lled in System Control Register in ARM core See note 1 VLPS VLPR Interrupt NOTE If VLPS was entered directly from RUN transition 7 hardware forces exit back to RUN and does not allow a transition to V...

Page 233: ...sequence to manage transitions safely The SMC manages the system s entry into and exit from all power modes This diagram illustrates the connections of the SMC with other system components in the chi...

Page 234: ...on to stop mode regulation After this point the interrupt is ignored until the PMC has completed its transition to stop mode regulation When an aborted stop mode entry sequence occurs SMC_PMCTRL STOPA...

Page 235: ...rresponding clock gating control bits in the SIM s registers Before entering this mode the following conditions must be met The MCG must be configured in a mode which is supported during VLPR See the...

Page 236: ...ntinue to be clocked provided they are enabled Clock gating to the peripheral is enabled via the SIM module When an interrupt request occurs the CPU exits WAIT mode and resumes processing in RUN mode...

Page 237: ...e retention versus functional needs and recovery time may be traded off NOTE All clock monitors must be disabled before entering these low power modes Stop VLPS VLPR VLPW LLSand VLLSx The various stop...

Page 238: ...entered directly from RUN mode exit to VLPR is disabled by hardware and the system will always exit back to RUN In VLPS the on chip voltage regulator remains in its stop regulation state as in VLPR A...

Page 239: ...p On Exit mode the SLEEPDEEP bit is set in the System Control Register in the ARM core and The device is configured as shown in Table 14 2 In VLLS the on chip voltage regulator is in its stop regulati...

Page 240: ...available while the MCU is in LLS or VLLS modes LLS is a state retention mode and all debug operation can continue after waking from LLS even in cases where system wakeup is due to a system reset even...

Page 241: ...ect LVD system This device includes a system to guard against low voltage conditions This protects memory contents and controls MCU system states during supply voltage variations The system is compris...

Page 242: ...t until the supply voltage rises above this threshold The LVD field in the SRS register of the RCM module RCM_SRS LVD is set following an LVD or power on reset 15 3 2 LVD interrupt operation By config...

Page 243: ...ded 15 5 Memory map and register descriptions Details about the PMC registers can be found here NOTE Different portions of PMC registers are reset only by particular reset types Each register s descri...

Page 244: ...The register s other bits are reset on Chip Reset Not VLLS For more information about these reset types refer to the Reset section details Address 4007_D000h base 0h offset 4007_D000h Bit 7 6 5 4 3 2...

Page 245: ...ontrol 2 register PMC_LVDSC2 This register contains status and control bits to support the low voltage warning function While the device is in the very low power or low leakage modes the LVD system is...

Page 246: ...erved This field is reserved This read only field is reserved and always has the value 0 LVWV Low Voltage Warning Voltage Select Selects the LVW trip point voltage VLVW The actual voltage for the warn...

Page 247: ...Isolation Reading this field indicates whether certain peripherals and the I O pads are in a latched state as a result of having been in a VLLS mode Writing 1 to this field when it is set releases the...

Page 248: ...Memory map and register descriptions KL27 Sub Family Reference Manual Rev 5 01 2016 248 Freescale Semiconductor Inc...

Page 249: ...gister descriptions found here describe the registers using byte addresses The registers can be written only when in supervisor mode MCM memory map Absolute address hex Register name Width in bits Acc...

Page 250: ...to AXBS input port n is absent 1 A bus slave connection to AXBS input port n is present 16 2 2 Crossbar Switch AXBS Master Configuration MCM_PLAMC PLAMC is a 16 bit read only register identifying the...

Page 251: ...tes for the speculation buffer DFCS EFDS Description 0 0 Speculation buffer is on for instruction and off for data 0 1 Speculation buffer is on for instruction and on for data 1 X Speculation buffer i...

Page 252: ...he stall mechanism allows software to execute code from the same block on which flash operations are being performed However software must ensure the sector the flash operations are being performed on...

Page 253: ...DFCDA Disable Flash Controller Data Caching Disables flash controller data caching 0 Enable flash controller data caching 1 Disable flash controller data caching 10 CFCC Clear Flash Controller Cache...

Page 254: ...ead only field is reserved and always has the value 0 2 CPOWOI Compute Operation Wake up on Interrupt 0 No effect 1 When set the CPOREQ is cleared on any interrupt or exception vector fetch 1 CPOACK C...

Page 255: ...descriptions continued Field Description 0 Request is cleared 1 Request Compute Operation Chapter 16 Miscellaneous Control Module MCM KL27 Sub Family Reference Manual Rev 5 01 2016 Freescale Semicond...

Page 256: ...Memory map register descriptions KL27 Sub Family Reference Manual Rev 5 01 2016 256 Freescale Semiconductor Inc...

Page 257: ...A 2 USB 3 17 1 2 Crossbar switch slave assignments This device contains 3 slaves connected to the crossbar switch The slave assignment is as follows Slave module Slave port number Flash memory control...

Page 258: ...onfiguration registers Please see the chip specific information for information on whether the arbitration method in the crossbar switch is programmable and by which module 17 4 Functional Description...

Page 259: ...ess to a slave port the crossbar drives IDLE transfers onto the slave bus even though a default master may be granted access to the slave port When a slave bus is being idled by the crossbar it remain...

Page 260: ...cenarios based on the requesting master port Table 17 1 How the Crossbar Switch grants control of a slave port to a master When Then the Crossbar Switch grants control to the requesting master Both of...

Page 261: ...last master of the slave port was master 1 and master 0 4 and 5 make simultaneous requests they are serviced in the order 4 then 5 then 0 The round robin arbitration mode generally provides a more fai...

Page 262: ...Initialization application information KL27 Sub Family Reference Manual Rev 5 01 2016 262 Freescale Semiconductor Inc...

Page 263: ...nputs as wakeup sources to the LLWU module LLWU_Px are external pin inputs and LLWU_M0IF M7IF are connections to the internal peripheral interrupt flags NOTE In addition to the LLWU wakeup sources the...

Page 264: ...ower modes and causes the MCU to exit both LLS and VLLS through a reset flow The LLWU module also includes two optional digital pin filters for the external wakeup pins See AN4503 Power Management for...

Page 265: ...w when exiting LLS NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit Stop mode on an LLS recovery 18 2 2 2 VLLS modes All...

Page 266: ...ces exit low leakge mode interrupt flow reset flow LLWU_P0 LLWU_P15 Pin filter 1 wakeup occurred Interrupt module flag detect WUPE15 2 Edge detect enter low leakge mode WUPE0 Edge detect Module7 inter...

Page 267: ...sed exit from a low leakage power mode includes external pin or internal module interrupt Wake up pin filter enable registers NOTE The LLWU registers can be written only in supervisor mode Write acces...

Page 268: ...select the edge detect type for the external wakeup input pins LLWU_P3 LLWU_P0 NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS It is unaffected b...

Page 269: ...pin enabled with falling edge detection 11 External input pin enabled with any change detection 18 4 2 LLWU Pin Enable 2 register LLWU_PE2 LLWU_PE2 contains the field to enable and select the edge de...

Page 270: ...enabled with any change detection WUPE4 Wakeup Pin Enable For LLWU_P4 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin...

Page 271: ...led as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection WUPE8 Wak...

Page 272: ...E13 Wakeup Pin Enable For LLWU_P13 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection...

Page 273: ...ag not used as wakeup source 1 Internal module flag used as wakeup source 4 WUME4 Wakeup Module Enable For Module 4 Enables an internal module as a wakeup source input 0 Internal module flag not used...

Page 274: ...et not VLLS and by reset types that trigger Chip Reset not VLLS It is unaffected by reset types that do not trigger Chip Reset not VLLS See the Introduction details for more information Address 4007_C...

Page 275: ...r the flag write a 1 to WUF3 0 LLWU_P3 input was not a wake up source 1 LLWU_P3 input was a wake up source 2 WUF2 Wakeup Flag For LLWU_P2 Indicates that an enabled external wakeup pin was a source of...

Page 276: ...10 WUF9 WUF8 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F2 field descriptions Field Description 7 WUF15 Wakeup Flag For LLWU_P15 Indicates that an enabled external wakeup pin was...

Page 277: ...source of exiting a low leakage power mode To clear the flag write a 1 to WUF9 0 LLWU_P9 input was not a wakeup source 1 LLWU_P9 input was a wakeup source 0 WUF8 Wakeup Flag For LLWU_P8 Indicates tha...

Page 278: ...sm 0 Module 6 input was not a wakeup source 1 Module 6 input was a wakeup source 5 MWUF5 Wakeup flag For module 5 Indicates that an enabled internal peripheral was a source of exiting a low leakage po...

Page 279: ...0 Module 0 input was not a wakeup source 1 Module 0 input was a wakeup source 18 4 9 LLWU Pin Filter 1 register LLWU_FILT1 LLWU_FILT1 is a control and status register that is used to enable disable t...

Page 280: ...LLWU_FILT2 is a control and status register that is used to enable disable the digital filter 2 features for an external pin NOTE This register is reset on Chip Reset not VLLS and by reset types that...

Page 281: ...only in LLS and VLLSx modes The LLWU module contains pin enables for each external pin and internal module For each external pin the user can disable or select the edge type for the wakeup with the f...

Page 282: ...ins with a reset vector fetch 18 5 3 Initialization For an enabled peripheral wakeup input the peripheral flag must be cleared by software before entering LLS or VLLSx mode to avoid an immediate exit...

Page 283: ...rface to an interface that can access most of the slave peripherals on this chip The peripheral bridge occupies 64 MB of the address space which is divided into peripheral slots of 4 KB It might be po...

Page 284: ...ripheral Access Control Register AIPS_PACRC 32 R W See section 19 3 2 286 2C Peripheral Access Control Register AIPS_PACRD 32 R W See section 19 3 2 286 40 Peripheral Access Control Register AIPS_ 32...

Page 285: ...usted For Writes Determines whether the master is trusted for write accesses 0 This master is not trusted for write accesses 1 This master is trusted for write accesses 28 MPL0 Master 0 Privilege Leve...

Page 286: ...for write accesses 16 MPL3 Master 3 Privilege Level Specifies how the privilege level of the master is determined 0 Accesses from this master are forced to user mode 1 Accesses from this master are no...

Page 287: ...ripheral is write protected 28 TP0 Trusted Protect Determines whether the peripheral allows accesses from an untrusted master When this field is set and an access is attempted by an untrusted master t...

Page 288: ...with an error response and no peripheral access initiates 0 This peripheral allows write accesses 1 This peripheral is write protected 20 TP2 Trusted Protect Determines whether the peripheral allows a...

Page 289: ...n error response and no peripheral access initiates 0 This peripheral allows write accesses 1 This peripheral is write protected 12 TP4 Trusted Protect Determines whether the peripheral allows accesse...

Page 290: ...with an error response and no peripheral access initiates 0 This peripheral allows write accesses 1 This peripheral is write protected 4 TP6 Trusted Protect Determines whether the peripheral allows ac...

Page 291: ...ge functions as a bus protocol translator between the crossbar switch and the slave peripheral bus The peripheral bridge manages all transactions destined for the attached slave devices and generates...

Page 292: ...Functional description KL27 Sub Family Reference Manual Rev 5 01 2016 292 Freescale Semiconductor Inc...

Page 293: ...ation as indicated by the last column in the following DMA source assignment table Table 20 1 DMA request sources MUX 0 Source number Source module Source description Async DMA capable 0 Channel disab...

Page 294: ...PM0 Channel 5 Yes 30 Reserved 31 Reserved 32 TPM1 Channel 0 Yes 33 TPM1 Channel 1 Yes 34 TPM2 Channel 0 Yes 35 TPM2 Channel 1 Yes 36 Reserved 37 Reserved 38 Reserved 39 Reserved 40 ADC0 Yes 41 Reserve...

Page 295: ...0 or any of the reserved sources disables that DMA channel 20 1 2 DMA transfers via PIT trigger The PIT module can trigger a DMA transfer on the first two DMA channels The assignments are detailed at...

Page 296: ...always on slots can be routed to four channels four independently selectable DMA channel routers The first two channels additionally provide a trigger functionality Each channel router can be assigne...

Page 297: ...upt timer PIT This mode is available only for channels 0 1 20 3 External signal description The DMAMUX has no external pins 20 4 Memory map register definition This section provides a detailed descrip...

Page 298: ...annel 0 Triggering is disabled If triggering is disabled and ENBL is set the DMA Channel will simply route the specified source to the DMA channel Normal mode 1 Triggering is enabled If triggering is...

Page 299: ...r packets at fixed intervals without the need for processor intervention The trigger is generated by the periodic interrupt timer PIT as such the configuration of the periodic triggering interval is d...

Page 300: ...been seen This is illustrated in the following figure DMA request Peripheral request Trigger Figure 20 3 DMAMUX channel triggering normal operation After the DMA request has been serviced the periphe...

Page 301: ...od to periodically read data from external devices and transfer the results into memory without processor intervention Using the GPIO ports to drive or sample waveforms By configuring the DMA to trans...

Page 302: ...e software should initiate the start of a DMA transfer an always enabled DMA source can be used to provide maximum flexibility When activating a DMA channel via software subsequent executions of the m...

Page 303: ...before use 20 6 2 Enabling and configuring sources To enable a source with periodic triggering 1 Determine with which DMA channel the source will be associated Note that only the first 2 DMA channels...

Page 304: ...hannel 3 Write 0x85 to CHCFG1 The following code example illustrates steps 1 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits vo...

Page 305: ...ps 2 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits volatile unsigned char CHCFG0 volatile unsigned char DMAMUX_BASE_ADDR 0x00...

Page 306: ...In File main c include registers h CHCFG8 0x00 CHCFG8 0x87 Initialization application information KL27 Sub Family Reference Manual Rev 5 01 2016 306 Freescale Semiconductor Inc...

Page 307: ...an efficient way to move blocks of data with minimal processor interaction The DMA module shown in the following figure has four channels that allow 8 bit 16 bit or 32 bit data transfers Each channel...

Page 308: ...nel Attributes MUX Control Arbitraton Control Data Path Control Figure 21 1 4 Channel DMA Block Diagram The terms peripheral request and DREQ refer to a DMA request from one of the on chip peripherals...

Page 309: ...MA in this chapter apply to any of the channels It is not possible to address all four channels at once As soon as a channel has been initialized it may be started by setting DCRn START or a properly...

Page 310: ...e operation is finished successfully or due to an error The channel indicates the operation status in the channel s DSR described in the definitions of the DMA Status Registers DSRn and Byte Count Reg...

Page 311: ...Control Register DMA_DCR2 32 R W 0000_0000h 21 3 4 315 4000_8130 Source Address Register DMA_SAR3 32 R W 0000_0000h 21 3 1 311 4000_8134 Destination Address Register DMA_DAR3 32 R W 0000_0000h 21 3 2...

Page 312: ...tten to bits 31 20 of this register see the value list in the field description A write of any other value to these bits causes a configuration error when the channel starts to execute For more inform...

Page 313: ...pletion of the write transfer BCRn decrements by 1 2 or 4 for 8 bit 16 bit or 32 bit accesses respectively BCRn is cleared if a 1 is written to DSR DONE In response to an event the DMA controller writ...

Page 314: ...is cleared at hardware reset or by writing a 1 to DONE 0 No bus error occurred 1 The DMA channel terminated with a bus error during the read portion of a transfer 28 BED Bus Error on Destination BED i...

Page 315: ...itten with a value equal to or less than 0F_FFFFh After being written with a value in this range bits 23 20 of BCR read back as 0000b A write to BCR of a value greater than 0F_FFFFh causes a configura...

Page 316: ...ource accesses are auto aligned otherwise destination accesses are auto aligned Source alignment takes precedence over destination alignment If auto alignment is enabled the appropriate address regist...

Page 317: ...r size The value of this boundary is based upon the initial source address SAR The base address should be aligned to a 0 modulo circular buffer size boundary Misaligned buffers are not possible The bo...

Page 318: ...erved This read only field is reserved and always has the value 0 5 4 LINKCC Link Channel Control Allows DMA channels to have their transfers linked The current DMA channel triggers a DMA request to t...

Page 319: ...sfer occurs DSRn CE is set and depending on the DCR configuration an interrupt event may be issued If the auto align bit DCRn AA is set error checking is performed on the appropriate registers A read...

Page 320: ...ation describing configuration request generation method and pointers to the data to be moved 21 4 2 1 Channel prioritization The four DMA channels are prioritized based on number with channel 0 havin...

Page 321: ...d with the total number of bytes to be transferred It is decremented by 1 2 or 4 at the end of each transfer depending on the transfer size DSRn DONE must be cleared for channel startup After the chan...

Page 322: ...nsfer is initiated if continuous mode is enabled DCRn CS 0 If a termination error occurs DSRn BED DONE are set and DMA transactions stop 21 4 4 Advanced Data Transfer Controls Auto Alignment Typically...

Page 323: ...t size allowed based on the address but not exceeding the configured size 21 4 5 Termination An unsuccessful transfer can terminate for one of the following reasons Error conditions When the DMA encou...

Page 324: ...Functional Description KL27 Sub Family Reference Manual Rev 5 01 2016 324 Freescale Semiconductor Inc...

Page 325: ...reset status information and reset filter control NOTE The RCM registers can be written only in supervisor mode Write accesses in user mode are blocked and will result in a bus error RCM memory map A...

Page 326: ...keup due to other wakeup sources 0x01 Other reset a bit is set if its corresponding reset source caused the reset Address 4007_F000h base 0h offset 4007_F000h Bit 7 6 5 4 3 2 1 0 Read POR PIN WDOG 0 0...

Page 327: ...Indicates a reset has been caused by an enabled LLWU module wakeup source while the chip was in a low leakage mode In LLS mode the RESET pin is the only wakeup source that can cause this reset Any en...

Page 328: ...a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM AP Control Register 0 Reset not caused by host debugger system setting of the System Reset Reque...

Page 329: ...hould be reconfigured before clearing PMC_REGSC ACKISO 0 All filtering disabled 1 LPO clock filter enabled RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes Selects how the reset pin filter is e...

Page 330: ...unt is 12 01100 Bus clock filter count is 13 01101 Bus clock filter count is 14 01110 Bus clock filter count is 15 01111 Bus clock filter count is 16 10000 Bus clock filter count is 17 10001 Bus clock...

Page 331: ...subsequent system resets 00 No effect 01 Force boot from ROM with RCM_MR 1 set 10 Force boot from ROM with RCM_MR 2 set 11 Force boot from ROM with RCM_MR 2 1 set 0 Reserved This field is reserved Th...

Page 332: ...et Status Register 0 RCM_SSRS0 This register includes status flags to indicate all reset sources since the last POR LVD or VLLS Wakeup that have not been cleared by software Software can clear the sta...

Page 333: ...1 Reset caused by LVD trip or POR 0 SWAKEUP Sticky Low Leakage Wakeup Reset Indicates a reset has been caused by an enabled LLWU modulewakeup source while the chip was in a low leakage mode In LLS mo...

Page 334: ...Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit in the MDM AP Control Register 0 Reset not caused by host debugger system setting of the System Re...

Page 335: ...of ADC channels present on the device is determined by the pinout of the specific device package and is shown in the following table Table 23 1 Number of KL27 ADC channels and ADC pins Device Number...

Page 336: ...ADC0_DP1 ADC0_SE1 00010 DAD2 ADC0_DP2 and ADC0_DM2 ADC0_DP2 ADC0_SE2 00011 DAD3 ADC0_DP3 and ADC0_DM3 ADC0_DP3 ADC0_SE3 001001 AD4a Reserved ADC0_DM0 ADC0_SE4a 001011 AD5a Reserved ADC0_DM1 ADC0_SE5a...

Page 337: ...u enable the bandgap buffer by setting the PMC_REGSC BGBE bit Refer to the device data sheet for the bandgap voltage VBG specification 23 1 4 ADC analog supply and reference connections This device in...

Page 338: ...12 bit 10 bit and 8 bit modes Output format in 2 s complement 16 bit sign extended for differential modes Output in right justified unsigned format for single ended Single or continuous conversion th...

Page 339: ...ADVINM ACFE 1 SC2 Rn RA CFG1 2 CLMx CLMx Compare true MCU STOP ADHWT AD4 AD23 TempP V REFH VALTH VREFL VALTL AIEN COCO trigger DIFF MODE CLPx PG MG PG MG CLPx Calibration OFS CALF CAL SC3 CV1 ACFGT AC...

Page 340: ...ts I ADn Single Ended Analog Channel Inputs I VREFSH Voltage Reference Select High I VREFSL Voltage Reference Select Low I VDDA Analog Power Supply I VSSA Analog Ground I 23 3 1 Analog Power VDDA The...

Page 341: ...ef Voltage High and the VDDA potential VREFH must never exceed VDDA Connect the ground references to the same voltage potential as VSSA 23 3 4 Analog Channel Inputs ADx The ADC module supports up to 2...

Page 342: ...ADC Plus Side General Calibration Value Register ADC0_CLPS 32 R W 0000_0020h 23 4 12 357 4003_B03C ADC Plus Side General Calibration Value Register ADC0_CLP4 32 R W 0000_0200h 23 4 13 357 4003_B040 A...

Page 343: ...ctively controlling a conversion is allowed and vice versa for any of the SC1n registers specific to this MCU Writing SC1A while SC1A is actively controlling a conversion aborts the current conversion...

Page 344: ...nversion is completed 6 AIEN Interrupt Enable Enables conversion complete interrupts When COCO becomes set while the respective AIEN is high an interrupt is asserted 0 Conversion complete interrupt is...

Page 345: ...When DIFF 0 AD11 is selected as input when DIFF 1 it is reserved 01100 When DIFF 0 AD12 is selected as input when DIFF 1 it is reserved 01101 When DIFF 0 AD13 is selected as input when DIFF 1 it is re...

Page 346: ...e expense of maximum clock speed 6 5 ADIV Clock Divide Select Selects the divide ratio used by the ADC to generate the internal clock ADCK 00 The divide ratio is 1 and the clock rate is input clock 01...

Page 347: ...be active prior to conversion start When it is selected and it is not active prior to a conversion start when CFG2 ADACKEN 0 the asynchronous clock is activated at the start of a conversion and deact...

Page 348: ...ed Configuration Configures the ADC for very high speed operation The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks 0 Normal co...

Page 349: ...bit single ended 0 0 0 0 D D D D D D D D D D D D Unsigned right justified 11 bit differential S S S S S S D D D D D D D D D D Sign extended 2 s complement 10 bit single ended 0 0 0 0 0 0 D D D D D D...

Page 350: ...are related to the ADC mode of operation The compare value 2 register CV2 is used only when the compare range function is enabled that is SC2 ACREN 1 Address 4003_B000h base 18h offset 4d i where i 0d...

Page 351: ...0 0 ADCx_SC2 field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 ADACT Conversion Active Indicates that a conversio...

Page 352: ...ionality based on the values placed in CV1 and CV2 3 ACREN Compare Function Range Enable Configures the compare function to check if the conversion result of the input being monitored is either betwee...

Page 353: ...ile the calibration is in progress and is cleared when the calibration sequence is completed CALF must be checked to determine the result of the calibration sequence Once started the calibration routi...

Page 354: ...les averaged 10 16 samples averaged 11 32 samples averaged 23 4 8 ADC Offset Correction Register ADCx_OFS The ADC Offset Correction Register OFS contains the user selected or calibration generated off...

Page 355: ...4003_B000h base 2Ch offset 4003_B02Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0...

Page 356: ...on values of varying widths CLP0 5 0 CLP1 6 0 CLP2 7 0 CLP3 8 0 CLP4 9 0 CLPS 5 0 and CLPD 5 0 CLPx are automatically set when the self calibration sequence is done that is CAL is cleared If these reg...

Page 357: ...PS Calibration Value Calibration Value 23 4 13 ADC Plus Side General Calibration Value Register ADCx_CLP4 For more information see CLPD register description Address 4003_B000h base 3Ch offset 4003_B03...

Page 358: ...0 CLP3 Calibration Value Calibration Value 23 4 15 ADC Plus Side General Calibration Value Register ADCx_CLP2 For more information see CLPD register description Address 4003_B000h base 44h offset 4003...

Page 359: ...P1 Calibration Value Calibration Value 23 4 17 ADC Plus Side General Calibration Value Register ADCx_CLP0 For more information see CLPD register description Address 4003_B000h base 4Ch offset 4003_B04...

Page 360: ...ress 4003_B000h base 54h offset 4003_B054h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLMD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 361: ...10 Reserved This field is reserved This read only field is reserved and always has the value 0 CLM4 Calibration Value Calibration Value 23 4 21 ADC Minus Side General Calibration Value Register ADCx_C...

Page 362: ...only field is reserved and always has the value 0 CLM2 Calibration Value Calibration Value 23 4 23 ADC Minus Side General Calibration Value Register ADCx_CLM1 For more information see CLMD register d...

Page 363: ...lock output enable is disabled or CFG2 ADACKEN 0 the module is in its lowest power state The ADC can perform an analog to digital conversion on any of the software selectable channels All modes perfor...

Page 364: ...clock source within the ADC module When the ADACK clock source is selected it is not required to be active prior to conversion start When it is selected and it is not active prior to a conversion star...

Page 365: ...available and hardware trigger is enabled that is SC2 ADTRG 1 a conversion is initiated on the rising edge of ADHWT after a hardware trigger select event that is ADHWTSn has occurred If a conversion i...

Page 366: ...CFG1 MODE and SC1n DIFF as shown in the description of CFG1 MODE Conversions can be initiated by a software or hardware trigger In addition the ADC module can be configured for Low power operation Lo...

Page 367: ...ered operation conversions begin after SC1A is written In hardware triggered operation conversions begin after a hardware trigger If continuous conversions are also enabled a new set of conversions to...

Page 368: ...top mode with ADACK or Alternate Clock Sources not enabled When a conversion is aborted the contents of the data registers Rn are not altered The data registers continue to be the values transferred a...

Page 369: ...nfiguration that is CFG2 ADHSC The frequency of the conversion clock that is fADCK CFG2 ADHSC is used to configure a higher clock input frequency This will allow faster overall conversion times To mee...

Page 370: ...der SFCAdder 1 x 0x 10 3 ADCK cycles 5 bus clock cycles 1 1 11 3 ADCK cycles 5 bus clock cycles1 1 0 11 5 s 3 ADCK cycles 5 bus clock cycles 0 x 0x 10 5 ADCK cycles 5 bus clock cycles 0 1 11 5 ADCK cy...

Page 371: ...CK cycles Note The ADCK frequency must be between fADCK minimum and fADCK maximum to meet ADC specifications 23 5 4 6 Conversion time examples The following examples use the Equation 1 on page 370 and...

Page 372: ...uration A configuration for long ADC conversion is 16 bit differential mode with the bus clock selected as the input clock source The input clock divide by 8 ratio selected Bus frequency of 8 MHz Long...

Page 373: ...K cycles 5 bus clock cycles AverageNum 1 BCT 17 ADCK cycles LSTAdder 0 ADCK cycles HSCAdder 2 The resulting conversion time is generated using the parameters listed in in the preceding table Therefore...

Page 374: ...e input is sampled and converted the compare values in CV1 and CV2 are used as described in the following table There are six Compare modes as shown in the following table Table 23 13 Compare modes SC...

Page 375: ...ile the MCU is in Wait or Normal Stop modes The ADC interrupt wakes the MCU when the compare condition is met 23 5 6 Calibration function The ADC contains a self calibration function that is required...

Page 376: ...ar and SC3 CALF to set At the end of a calibration sequence SC1n COCO will be set SC1n AIEN can be used to allow an interrupt to occur at the end of a calibration sequence At the end of the calibratio...

Page 377: ...e of operation The formatting of the OFS is different from the data result register Rn to preserve the resolution of the calibration value regardless of the conversion mode selected Lower order bits a...

Page 378: ...user defined offset For applications that may change the offset repeatedly during operation store the initial offset calibration value in flash so it can be recovered and added to any user offset adj...

Page 379: ...K are available as conversion clock sources while in Wait mode The use of ALTCLK as the conversion clock source in Wait is dependent on the definition of ALTCLK for this MCU See the Chip Configuration...

Page 380: ...rom Normal Stop mode if the respective ADC interrupt is enabled that is when SC1n AIEN 1 The result register Rn will contain the data from the first completed conversion that occurred during Normal St...

Page 381: ...complete conversions an initialization procedure must be performed A typical sequence is 1 Calibrate the ADC by following the calibration instructions in Calibration function 2 Update CFG to select th...

Page 382: ...CT 0 Flag indicates if a conversion is in progress Bit 6 ADTRG 0 Software trigger selected Bit 5 ACFE 0 Compare function disabled Bit 4 ACFGT 0 Not used in this example Bit 3 ACREN 0 Compare range dis...

Page 383: ...dded control applications requiring an ADC For guidance on selecting optimum external component values and converter parameters see AN4373 Cookbook for SAR ADC Measurements 23 7 1 External pins and ro...

Page 384: ...erence The two pairs are external VREFH and VREFL and alternate VALTH and VALTL These voltage references are selected using SC2 REFSEL The alternate voltage reference pair VALTH and VALTL may select a...

Page 385: ...tween VREFH and VREFL If the input is equal to or exceeds VREFH the converter circuit converts the signal to 0xFFF which is full scale 12 bit representation 0x3FF which is full scale 10 bit representa...

Page 386: ...t mode 12 in 12 bit mode or 16 in 16 bit mode 23 7 2 3 Noise induced errors System noise that occurs during the sample or conversion process can affect the accuracy of the conversion The ADC accuracy...

Page 387: ...me error Reduce the effect of synchronous noise by operating off the asynchronous clock that is ADACK and averaging Noise that is synchronous to ADCK cannot be averaged out 23 7 2 4 Code width and qua...

Page 388: ...ferential non linearity DNL This error is defined as the worst case difference between the actual code width and the ideal code width for all conversions Integral non linearity INL This error is defin...

Page 389: ...ity occurs when except for code jitter the converter converts to a lower code for a higher input voltage Missing codes Missing codes are those values never converted for any input value In 8 bit or 10...

Page 390: ...Application information KL27 Sub Family Reference Manual Rev 5 01 2016 390 Freescale Semiconductor Inc...

Page 391: ...needed for internal connection to the CMP The CMP can be optionally on in all modes except VLLS0 The CMP has several module to module interconnects in order to facilitate ADC triggering TPM triggerin...

Page 392: ...version using this same reference at the same time is negatively impacted VDD Vin2 input 24 1 4 CMP trigger mode The CMP and 6 bit DAC sub block supports trigger mode operation when CMP_CR1 TRIGM is s...

Page 393: ...f the supply voltage The 6 bit DAC is 64 tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed The 64 tap resistor ladder network...

Page 394: ...trigger a DMA transfer Functional in all modes of operation The filter functions are not available in the following modes Stop VLPS LLS VLLSx 24 2 2 6 bit DAC key features The 6 bit DAC has the follow...

Page 395: ...Q ANMUX MSEL 2 0 CMP CMP MUX DAC output DACEN Vin1 Vin2 Window and filter control CMPO Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Refer...

Page 396: ...ndow Control block is bypassed when CR1 WE 0 The Filter block is bypassed when not in use The Filter block acts as a simple sampler if the filter is bypassed and CR0 FILTER_CNT is set to 0x01 The Filt...

Page 397: ...d This read only field is reserved and always has the value 0 6 4 FILTER_CNT Filter Sample Count Represents the number of consecutive samples that must agree prior to the comparator ouput filter accep...

Page 398: ...ble The CMP does not support window compare function and a 0 must always be written to WE 0 Windowing mode is not selected 1 Windowing mode is selected 5 TRIGM Trigger Mode Enable CMP and DAC are conf...

Page 399: ...s no effect 1 CMPO is available on the associated CMPO output pin The comparator output CMPO is driven out on the associated CMPO output pin if the comparator owns the pin If the comparator does not o...

Page 400: ...ll be asserted when CFR is set 0 Interrupt is disabled 1 Interrupt is enabled 3 IEF Comparator Interrupt Enable Falling Enables the CFF interrupt from the CMP When this field is set an interrupt will...

Page 401: ...is powered down to conserve power 0 DAC is disabled 1 DAC is enabled 6 VRSEL Supply Voltage Reference Source Select 0 Vin1 is selected as resistor ladder network supply reference 1 Vin2 is selected a...

Page 402: ...g a noise generator 000 IN0 001 IN1 010 IN2 011 IN3 100 IN4 101 IN5 110 IN6 111 IN7 MSEL Minus Input Mux Control Determines which input is selected for the minus input of the comparator For INx inputs...

Page 403: ...eatures can be combined as shown in the following table Individual modes are discussed below Table 24 2 Comparator sample filter controls Mode CR1 EN CR1 WE CR1 SE CR0 FILTER_C NT FPR FILT_PER Operati...

Page 404: ...ntinuous mode s 2A 2B IRQ Internal bus INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 1 WE 0 SE CGMUX COS FILT_PER 0 FILT_PER COS IER F CFR F WINDOW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 divided...

Page 405: ...e The path from analog inputs to COUTA is combinational unclocked Windowing control is completely bypassed COUTA is sampled whenever a rising edge is detected on the filter block clock input The compa...

Page 406: ...E EN PMODE HYSTCTR 1 0 divided bus clock CMPO 0x01 Internal bus Polarity select Window control Filter block Interrupt control Clock prescaler To other SOC functions 0 Figure 24 5 Sampled Filtered 4B s...

Page 407: ...s limited to Low Speed mode regardless of CR1 PMODE setting Windowed Sampled and Filtered modes are not supported The CMP output pin is latched and does not reflect the compare output state The positi...

Page 408: ...register bit values They also apply to COUT for all sampling modes Filtering can be performed using an internal timebase defined by FPR FILT_PER to determine sample time The need for digital filtering...

Page 409: ...R_CNT must also be traded off against the desire for minimal latency in recognizing actual comparator output transitions The probability of detecting an actual output change within the nominal latency...

Page 410: ...SCR IEF or both the corresponding change on COUT forces a DMA transfer request rather than a CPU interrupt instead When the DMA has completed the transfer it sends a transfer completing indicator that...

Page 411: ...ntains a 64 tap resistor ladder network and a 64 to 1 multiplexer which selects an output voltage from one of 64 distinct levels that outputs from DACO It is controlled through the DAC Control Registe...

Page 412: ...as no interrupts 24 13 CMP Trigger Mode CMP and DAC are configured to CMP Trigger mode when CMP_CR1 TRIGM is set to 1 In addition the CMP must be enabled If the DAC is to be used as a reference to the...

Page 413: ...ures of the DAC module include On chip programmable reference generator output The voltage output range is from 1 4096 Vin to Vin and the step is 1 4096 Vin where Vin is the input voltage Vin can be s...

Page 414: ...BF DACBBIEN OR dac_interrupt DACTRGSE LPEN DACRFS DACREF_1 Vin Vo Data Buffer Figure 25 1 DAC block diagram 25 4 Memory map register definition The DAC has registers to control analog comparator and p...

Page 415: ...ess 4003_F000h base 0h offset 2d i where i 0d to 1d Bit 7 6 5 4 3 2 1 0 Read DATA0 Write Reset 0 0 0 0 0 0 0 0 DACx_DATnL field descriptions Field Description DATA0 DATA0 When the DAC buffer is not en...

Page 416: ...eld is reserved This read only field is reserved and always has the value 0 1 DACBFRPTF DAC Buffer Read Pointer Top Position Flag In FIFO mode it is FIFO nearly empty flag It is set when only one data...

Page 417: ...d and buffer is enabled writing 1 to this field will advance the buffer read pointer once 0 The DAC soft trigger is not valid 1 The DAC soft trigger is valid 3 LPEN DAC Low Power Control NOTE See the...

Page 418: ...01 Reserved 10 One Time Scan mode 11 FIFO mode 0 DACBFEN DAC Buffer Enable 0 Buffer read pointer is disabled The converted data is always the first word of the buffer 1 Buffer read pointer is enabled...

Page 419: ...nce inputs DACREF_1 and DACREF_2 as the DAC reference voltage Vin by C0 DACRFS See the chip specific DAC information to determine the source options for DACREF_1 and DACREF_2 When the DAC is enabled i...

Page 420: ...mode the buffer is organized as a FIFO For a valid write to any DACDATx the data is put into the FIFO and the write pointer is automatically incremented The module is connected internally to a 32bit...

Page 421: ...e default mode and is disabled 25 5 4 Low Power mode operation The following table shows the wait mode and the stop mode operation of the DAC module Table 25 2 Modes of operation Modes of operation De...

Page 422: ...Functional description KL27 Sub Family Reference Manual Rev 5 01 2016 422 Freescale Semiconductor Inc...

Page 423: ...to analog peripherals such as the ADC DAC or CMP The voltage reference has three operating modes that provide different levels of supply rejection and power consumption The following figure is a bloc...

Page 424: ...election Off Bandgap enabled standby output buffer disabled Low power buffer mode output buffer enabled High power buffer mode output buffer enabled 1 2 V output at room temperature Dedicated output p...

Page 425: ...the Voltage Reference signals properties Table 26 1 VREF Signal Descriptions Signal Description I O VREF_OUT Internally generated Voltage Reference output O NOTE When the VREF output buffer is disable...

Page 426: ...REF voltage This bit should be written to 1 to achieve the performance stated in the data sheet If the chop oscillator is to be used in very low power modes the system bandgap voltage reference must a...

Page 427: ...ernal supply noise and variation If it is desired to keep the regulator enabled in very low power modes refer to the Chip Configuration details for a description on how this can be achieved This bit s...

Page 428: ...following table shows all possible function configurations of the Voltage Reference Table 26 2 Voltage Reference function configurations SC VREFEN SC MODE_LV Configuration Functionality 0 X Voltage Re...

Page 429: ...lue This is the buffer start up delay Tstup and the value is specified in the appropriate device data sheet 26 3 2 2 SC MODE_LV 01 The internal VREF bandgap is on The high power buffer is enabled to g...

Page 430: ...required to connect between the VREF_OUT pin and VSSA 26 3 2 4 SC MODE_LV 11 Reserved 26 4 Internal voltage regulator The VREF module contains an internal voltage regulator that can be enabled to prov...

Page 431: ...stup and the value is specified in the appropriate device data sheet Also there will be some settling time when a step change of the load current is applied to the VREF_OUT pin When the 1 75V VREF reg...

Page 432: ...Initialization Application Information KL27 Sub Family Reference Manual Rev 5 01 2016 432 Freescale Semiconductor Inc...

Page 433: ...USB recovery feature Low frequency Internal Reference Clock LIRC Selectable 8 MHz or 2 MHz clock source Trim bit to ensure 3 accuracy across PVT Glitchless clock switcher for internal clock sources H...

Page 434: ...K MCGIRCLK LIRC_DIV1_CLK MCGOUTCLK MCGPCLK Figure 27 1 MCG_Lite block diagram 27 2 Memory map and register definition The MCG_Lite module contains several fields for selecting the clock source and the...

Page 435: ...urce Select Selects the clock source for MCGOUTCLK 00 Selects HIRC clock as the main clock source This is HIRC mode 01 Selects LIRC clock as the main clock source This is LIRC2M or LIRC8M mode 10 Sele...

Page 436: ...the crystal oscillator or the external clock source 11 Very high frequency range selected for the crystal oscillator or the external clock source Same effect as 10 3 HGO0 Crystal Oscillator Operation...

Page 437: ...Lite works at EXT mode 11 Reserved 1 OSCINIT0 OSC Initialization Status This flag which resets to 0 is set to 1 after the initialization cycles of the crystal oscillator clock are completed After bein...

Page 438: ...HIRCEN 0 LIRC_DIV2 Write Reset 0 0 0 0 0 0 0 0 MCG_MC field descriptions Field Description 7 HIRCEN High frequency IRC Enable Enables the HIRC even when MCG_Lite is not working at HIRC mode 0 HIRC sou...

Page 439: ...ode If entering VLPR mode MCG_Lite has to be configured and enter LIRC2M LIRC8M or EXT mode and MCG_MC HIRCEN must also be cleared After it enters VLPR mode writes to any of the MCG control registers...

Page 440: ...tion of MCG_SC FCRDIV The divided clock of LIRC DIV1 is one of the inputs of clock select switch It is the input for the 2nd LIRC DIV as well See the Chip Configuration information for more details 27...

Page 441: ...speed USB IRC 48 MHz accuracy is 1 5 after factory trim The USB module monitors the accuracy of the nominal 48 MHz clock and adjusts the Fine Trim based on the default Fine Trim value input which is...

Page 442: ...Functional description KL27 Sub Family Reference Manual Rev 5 01 2016 442 Freescale Semiconductor Inc...

Page 443: ...riding control over the MCG_Lite and OSC_CR enable functions When RTC_CR OSCE is set the OSC is configured for low frequency low power and RTC_CR SCxP override OSC_CR SCxP to control the internal capa...

Page 444: ...ration in more detail 28 4 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals Three clocks are output from OSC module OSCCLK for MCU system OS...

Page 445: ...able found here shows the user accessible signals available for the OSC module Refer to signal multiplexing information for this MCU for more details Table 28 1 OSC Signal Descriptions Signal Descript...

Page 446: ...igh gain Connection 3 1 With the low power mode the oscillator has the internal feedback resistor RF Therefore the feedback resistor must not be externally with the Connection 3 2 When the load capaci...

Page 447: ...ound here NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it OSC VSS Clock Input I O XTAL EXTAL Figure 28 5 External Clock Connections 28 8 Memory Map Register Defin...

Page 448: ...external reference clock OSCERCLK 0 External reference clock is inactive 1 External reference clock is enabled 6 Reserved This field is reserved This read only field is reserved and always has the val...

Page 449: ...oad 0 Disable the selection 1 Add 8 pF capacitor to the oscillator load 0 SC16P Oscillator 16 pF Capacitor Load Configure Configures the oscillator load 0 Disable the selection 1 Add 16 pF capacitor t...

Page 450: ...its 28 9 1 1 Off The OSC enters the Off state when the system does not require OSC clocks Upon entering this state XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by...

Page 451: ...CLK_OUT Its frequency is determined by the external components being used 28 9 1 4 External Clock mode The OSC enters external clock state when it is enabled and external reference clock selection bit...

Page 452: ...al capacitors could be used 28 9 2 2 Low Frequency Low Power Mode In low frequency low power mode the oscillator uses a gain control loop to minimize power consumption As the oscillation amplitude inc...

Page 453: ...age filtering and converts the output to logic levels 28 9 3 Counter The oscillator output clock OSC_CLK_OUT is gated off until the counter has detected 4096 cycles of its input clock XTL_CLK After 40...

Page 454: ...ister settings If CR ERCLKEN and CR EREFSTEN are set before entry to Low Leakage Stop modes the OSC is still functional in these modes After waking up from Very Low Leakage Stop VLLSx modes all OSC re...

Page 455: ...ol TPM1_C4SC TPM1 4003_9030 Channel n Value TPM1_C4V TPM1 4003_9034 Channel n Status and Control TPM1_C5SC TPM1 4003_9038 Channel n Value TPM1_C5V TPM1 4003_A01C Channel n Status and Control TPM2_C2SC...

Page 456: ...facilitate customer use cases For complete details on the TPM module interconnects please refer to the Module to Module section 29 1 2 Clock options The TPM blocks are clocked from a single TPM clock...

Page 457: ...erflow 1001 TPM1 overflow 1010 TPM2 overflow 1011 Reserved 1100 RTC alarm 1101 RTC seconds 1110 LPTMR trigger 1111 Reserved 29 1 4 Global timebase Each TPM has a global timebase feature controlled by...

Page 458: ...rt operation in low power modes by clocking the counter compare and capture registers from an asynchronous clock that can remain functional in low power modes 29 2 2 Features The TPM features include...

Page 459: ...til the core returns to normal user operating mode or to operate normally When the counter is paused trigger inputs and input capture events are ignored During doze mode the TPM can be configured to o...

Page 460: ...put compare EPWM and CPWM modes generation of channel 0 outputs signals in output compare EPWM and CPWM modes 1 2 4 8 16 32 64 or 128 3 Figure 29 1 TPM block diagram 29 3 TPM Signal Descriptions Table...

Page 461: ...T 32 R W 0000_0000h 29 4 2 464 4003_8008 Modulo TPM0_MOD 32 R W 0000_FFFFh 29 4 3 465 4003_800C Channel n Status and Control TPM0_C0SC 32 R W 0000_0000h 29 4 4 466 4003_8010 Channel n Value TPM0_C0V 3...

Page 462: ...US 32 R W 0000_0000h 29 4 6 468 4003_9070 Channel Polarity TPM1_POL 32 R W 0000_0000h 29 4 7 470 4003_9084 Configuration TPM1_CONF 32 R W 0000_0000h 29 4 8 471 4003_A000 Status and Control TPM2_SC 32...

Page 463: ...read only field is reserved and always has the value 0 8 DMA DMA Enable Enables DMA transfers for the overflow flag 0 Disables DMA transfers 1 Enables DMA transfers 7 TOF Timer Overflow Flag Set by ha...

Page 464: ...k domain 00 TPM counter is disabled 01 TPM counter increments on every TPM counter clock 10 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock 11 Reserved PS Pre...

Page 465: ...er The MOD register is updated with the value of its write buffer according to MOD Register Update Additional writes to the MOD write buffer are ignored until the register has been updated It is recom...

Page 466: ...Edge Only 11 Capture on Rising or Falling Edge 01 01 Output compare Toggle Output on match 10 Clear Output on match 11 Set Output on match 10 10 Edge aligned PWM High true pulses clear Output on match...

Page 467: ...nnel logic Its functionality is dependent on the channel mode When a channel is disabled this field will not change state until acknowledged in the TPM counter clock domain 4 MSA Channel Mode Select U...

Page 468: ...L Channel Value Captured TPM counter value of the input modes or the match value for the output modes This field must be written with single 16 bit or 32 bit access 29 4 6 Capture and Compare Status T...

Page 469: ...ter description 0 TPM counter has not overflowed 1 TPM counter has overflowed 7 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 CH5F Channel 5 Flag See...

Page 470: ...address 70h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 POL5 POL4 POL3 POL2 POL1 POL0 W Reset 0...

Page 471: ...CONF This register selects the behavior in debug and wait modes and the use of an external global time base Address Base address 84h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 TRGS...

Page 472: ...ernal channel pin input capture or external trigger sources When selecting an internal trigger the channel selected should be configured for input capture Only a rising edge input capture can be used...

Page 473: ...nting again The trigger input is ignored if the TPM counter is paused during debug mode or doze mode This field should only be changed when the TPM counter is disabled 0 TPM counter starts to incremen...

Page 474: ...requests The TPM counter clock domain is used to clock the counter and prescaler along with the output compare and input capture logic The TPM counter clock is considered asynchronous to the bus cloc...

Page 475: ...2 3 3 1 1 1 1 1 1 1 1 1 selected input clock prescaler counter timer module counting is up PS 2 0 001 CNTIN 0x0000 timer module counter Figure 29 2 Example of the Prescaler Counter 29 5 3 Counter The...

Page 476: ...and the TOF bit is set in each rising edge of the TPM counter clock 29 5 3 2 Up down counting Up down counting is selected when SC CPWMS 1 When configured for up down counting configuring CONF MOD to...

Page 477: ...r is not generating the global time base then it can be used as an independent counter or pulse accumulator The local TPM counter can also be configured to synchronize to the global time base by confi...

Page 478: ...e channel sources When CSOT 1 the counter will only start incrementing on a rising edge on the channel input provided ELSnA 1 When CROT 1 the counter will reset to zero on either edge of the channel i...

Page 479: ...mable position polarity duration and frequency When the counter matches the value in the CnV register of an output compare channel the channel n output can be set cleared or toggled if MSnB is clear I...

Page 480: ...l output channel n output CHnF bit TOF bit CNT MOD 0x0005 CnV 0x0003 counter overflow channel n match counter overflow channel n match counter overflow 0 1 2 3 4 5 0 1 2 3 4 5 0 1 previous value previ...

Page 481: ...ue in the CnV register the CHnF bit is set and the channel n interrupt is generated if CHnIE 1 however the channel n output is not controlled by TPM If ELSnB ELSnA 1 0 then the channel n output is for...

Page 482: ...2 MOD see the following figure MOD must be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results In the CPWM mode the TPM counter counts up until it re...

Page 483: ...figure TOF bit 7 8 8 7 7 7 6 6 6 5 5 5 4 4 3 3 2 2 1 0 1 previous value CNT channel n output counter overflow channel n match in down counting channel n match in up counting channel n match in down c...

Page 484: ...D to zero If the selected mode is CPWM then MOD register is updated after MOD register was written and the TPM counter changes from MOD to MOD 1 29 5 8 2 CnV Register Update If CMOD 1 0 0 0 then CnV r...

Page 485: ...red either by DMA transfer done or writing a one to CHnF TOF bit see the following table Table 29 7 Clear CHnF TOF Bit DMA How CHnF TOF Bit Can Be Cleared 0 CHnF TOF bit is cleared by writing a 1 to C...

Page 486: ...in input capture mode the channels outputs are zero the channels pins are not controlled by TPM ELS n B ELS n A 0 0 29 5 12 TPM Interrupts This section describes TPM interrupts 29 5 12 1 Timer Overflo...

Page 487: ...channel DMA channel number PIT Channel 0 DMA Channel 0 PIT Channel 1 DMA Channel 1 30 1 2 PIT ADC triggers PIT triggers are selected as ADCx trigger sources using the bits of SIM_SOPT7 ADCxTRGSEL For...

Page 488: ...gger DMA channels 30 2 1 Block diagram The following figure shows the block diagram of the PIT module Timer n Timer 1 PIT registers Peripheral bus load_value PIT Triggers Peripheral bus clock Interrup...

Page 489: ...0_0002h 30 4 1 490 4003_70E0 PIT Upper Lifetime Timer Register PIT_LTMR64H 32 R 0000_0000h 30 4 2 491 4003_70E4 PIT Lower Lifetime Timer Register PIT_LTMR64L 32 R 0000_0000h 30 4 3 491 4003_7100 Timer...

Page 490: ...MDIS FRZ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 PIT_MCR field descriptions Field Description 31 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 Reserve...

Page 491: ...riptions Field Description LTH Life Timer value Shows the timer value of timer 1 If this register is read at a time t1 LTMR64L shows the value of timer 0 at time t1 30 4 3 PIT Lower Lifetime Timer Reg...

Page 492: ...0 0 0 0 0 0 0 0 0 PIT_LDVALn field descriptions Field Description TSV Timer Start Value Sets the timer start value The timer will count down until it reaches 0 then it will generate an interrupt and...

Page 493: ...d descriptions Field Description 31 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 CHN Chain Mode When activated Timer n 1 needs to expire before timer...

Page 494: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIT_TFLGn field descriptions Field Description 31 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 TIF Timer Interr...

Page 495: ...read via the CVAL registers The counter period can be restarted by first disabling and then enabling the timer with TCTRLn TEN See the following figure p1 Timer enabled Disable timer p1 p1 Start valu...

Page 496: ...rupts can be enabled by setting TCTRLn TIE TFLGn TIF are set to 1 when a timeout occurs on the associated timer and are cleared to 0 by writing a 1 to the corresponding TFLGn TIF 30 5 3 Chained timers...

Page 497: ...TEN Timer 3 shall be used only for triggering Therefore Timer 3 is started by writing a 1 to TCTRL3 TEN TCTRL3 TIE stays at 0 The following example code matches the described setup turn on PIT PIT_MC...

Page 498: ...IT_LDVAL2 0x00000009 setup Timer 2 for 10 counts PIT_TCTRL2 TIE enable Timer 2 interrupt PIT_TCTRL2 CHN chain Timer 2 to Timer 1 PIT_TCTRL2 TEN start Timer 2 Timer 1 PIT_LDVAL1 0x23C345FF setup Timer...

Page 499: ...RL0 TEN start timer 0 To access the lifetime read first LTMR64H and then LTMR64L current_uptime PIT_LTMR64H 32 current_uptime current_uptime PIT_LTMR64L Chapter 30 Periodic Interrupt Timer PIT KL27 Su...

Page 500: ...Example configuration for the lifetime timer KL27 Sub Family Reference Manual Rev 5 01 2016 500 Freescale Semiconductor Inc...

Page 501: ...e clock the internal 1 kHz LPO OSCERCLK or an external 32 768 kHz crystal An interrupt is generated and the counter may reset when the counter equals the value in the 16 bit compare register 31 1 2 LP...

Page 502: ...VLLS0 mode See Clock Distribution for more details on these clocks 31 2 Introduction The low power timer LPTMR can be configured to operate as a time counter with optional prescaler or as a pulse coun...

Page 503: ...oes not increment in Time Counter mode 31 3 LPTMR signal descriptions Table 31 2 LPTMR signal descriptions Signal I O Description LPTMR0_ALTn I Pulse Counter Input pin 31 3 1 Detailed signal descripti...

Page 504: ...0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TCF TIE TPS TPP TFC TMS TEN W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPTMRx_CSR field descriptions Field Description 31 8 Reserved This field is res...

Page 505: ...set whenever TCF is set When set TFC configures the CNR to reset on overflow TFC must be altered only when the LPTMR is disabled 0 CNR is reset whenever TCF is set 1 CNR is reset on overflow 1 TMS Tim...

Page 506: ...r clock by 1024 glitch filter recognizes change on input pin after 512 rising clock edges 1010 Prescaler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 ris...

Page 507: ...R equals the value in the CMR and increments TCF is set and the hardware trigger asserts until the next time the CNR increments If the CMR is 0 the hardware trigger will remain asserted until the LPTM...

Page 508: ...t be set as the last step in the initialization This ensures the LPTMR is configured correctly and the LPTMR counter is reset to zero following a warm reset 31 5 2 LPTMR clocking The LPTMR prescaler g...

Page 509: ...clock cycle When the LPTMR is enabled the first increment will take an additional one or two prescaler clock cycles due to synchronization logic 31 5 3 3 Glitch filter In Pulse Counter mode when the g...

Page 510: ...is generated CNR is reset if CSR TFC is clear When the LPTMR is enabled the CMR can be altered only when CSR TCF is set When updating the CMR the CMR must be written and CSR TCF must be cleared befor...

Page 511: ...gger is always enabled When Then The CMR is set to 0 with CSR TFC clear The LPTMR hardware trigger will assert on the first compare and does not deassert The CMR is set to a nonzero value or if CSR TF...

Page 512: ...Functional description KL27 Sub Family Reference Manual Rev 5 01 2016 512 Freescale Semiconductor Inc...

Page 513: ...overrides the capacitor configurations So make sure to use low range crystal 30KHz 40KHz when using RTC_CR to configure the OSC 32 1 2 RTC_CLKOUT options RTC_CLKOUT pin can be driven either with the R...

Page 514: ...32 1 RTC signal descriptions Signal Description I O RTC_CLKOUT 1 Hz square wave output or OSCERCLK O 32 2 3 1 RTC clock output The clock to the seconds counter is available on the RTC_CLKOUT signal I...

Page 515: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TSR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TSR field descriptions Field Description TSR...

Page 516: ...ield descriptions Field Description TAR Time Alarm Register When the time counter is enabled the SR TAF is set whenever the TAR TAR equals the TSR TSR and the TSR TSR increments Writing to the TAR cle...

Page 517: ...o to configure for a compensation interval of one second This register is double buffered and writes do not take affect until the end of the current compensation interval TCR Time Compensation Registe...

Page 518: ...on 31 24 Reserved This field is reserved This read only field is reserved and always has the value 0 23 15 Reserved This field is reserved This read only field is reserved and always has the value 0 1...

Page 519: ...on 1 Wakeup pin instead outputs the RTC 32kHz clock provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals 3 UM Update Mode Allows SR TCE to be written even when the...

Page 520: ...has the value 0 2 TAF Time Alarm Flag Time alarm flag is set when the TAR TAR equals the TSR TSR and the TSR TSR increments This bit is cleared by writing the TAR register 0 Time alarm has not occurr...

Page 521: ...t locked and writes complete as normal 5 SRL Status Register Lock After being cleared this bit can be set only by POR or software reset 0 Status Register is locked and writes are ignored 1 Status Regi...

Page 522: ...evices Whenever the wakeup pin is enabled and this bit is set the wakeup pin will assert 0 No effect 1 If the wakeup pin is enabled then the wakeup pin will assert 6 5 Reserved This field is reserved...

Page 523: ...C registers to their default state A software reset bit can also initialize all RTC registers 32 4 1 1 Oscillator control The 32 768 kHz crystal oscillator is disabled at POR and must be enabled by so...

Page 524: ...register because the seconds register increments on the falling edge of bit 14 of the prescaler register The time prescaler register increments provided SR TCE is set SR TIF is clear SR TOF is clear...

Page 525: ...compensation value is used that is from once a second to once every 256 seconds Updates to the time compensation register will not take effect until the next time the time seconds register increments...

Page 526: ...ates to LR Write accesses to a locked register are ignored and do not generate a bus error 32 4 7 Interrupt The RTC interrupt is asserted whenever a status flag and the corresponding interrupt enable...

Page 527: ...lines for host mode functionality A 3 3 V regulator VBUS detect signal To detect a valid VBUS in device mode use a GPIO signal that can wake the chip in all power modes USB controller FS LS transceiv...

Page 528: ...n the application 33 1 3 1 AA AAA cells power supply The chip can be powered by two AA AAA cells In this case the MCU is powered through VDD which is within the 1 8 to 3 0 V range After USB cable inse...

Page 529: ...he battery charger USB Regulator USB XCVR USB Controller USB0_DM USB0_DP VDD VOUT33 VREGIN TYPE A D D VBUS Cstab To PMC and Pads Chip VSS Charger Li Ion Si2301 Figure 33 3 USB regulator Li ion usecase...

Page 530: ...USB2 0 full speed compliant peripheral and interfaces to a USBFS transceiver NOTE This chapter describes the following registers that have similar names USB_CTL USB_CTRL and USB_CONTROL These are all...

Page 531: ...token based protocol The bus allows peripherals to be attached configured used and detached while the host and other peripherals are in operation USB software provides a uniform view of the system fo...

Page 532: ...nterfaces Low power consumption with clock recovery is supported to eliminate the 48 MHz crystal It is used for USB device only implementation 33 3 Functional description USBFS communicates with the p...

Page 533: ...NONOTG Internal 15 k pulldown resistors on the USB_DP and USB_DM signals which are primarily intended for Host mode operation but are also useful in Device mode as explained below NOTE For device oper...

Page 534: ...h 16 fully bidirectional endpoints would require 512 bytes of system memory to implement the BDT The two BD entries allows for an EVEN BD and ODD BD entry for each endpoint direction This allows the m...

Page 535: ...is shown in the following diagram Current Endpoint BDT Buffer in Memory BDT Page Start of Buffer 000 ODD TX BDT_PAGE Registers END_POINT System Memory End of Buffer Figure 33 7 Buffer descriptor tabl...

Page 536: ...ether it owns the BD and corresponding buffer in system memory To compute the entry point into the BDT the BDT_PAGE registers are concatenated with the current endpoint and the TX and ODD fields to fo...

Page 537: ...received Where the buffer resides in system memory The format for the BD is shown in the following figure Table 33 4 Buffer descriptor format 31 26 25 16 15 8 7 6 5 4 3 2 1 0 RSVD BC 10 bits RSVD OWN...

Page 538: ...y this bit is 1 with ISO endpoints feeding a FIFO The microprocessor is not informed that a token has been processed the data is simply transferred to or from the FIFO When KEEP is set normally the NI...

Page 539: ...nsaction When USBFS transmits or receives data it computes the BDT address using the address generation shown in Addressing Buffer Descriptor Entries table If OWN 1 the following process occurs 1 USBF...

Page 540: ...Therefore in response to oversized packets the USB core continues ACKing the packet for non isochronous transfers Table 33 6 USB responses to DMA overrun errors Errors due to Memory Latency Errors du...

Page 541: ...t value Section page 4007_2000 Peripheral ID register USB0_PERID 8 R 04h 33 5 1 543 4007_2004 Peripheral ID Complement register USB0_IDCOMP 8 R FBh 33 5 2 543 4007_2008 Peripheral Revision register US...

Page 542: ...54 4007_20E4 Endpoint Control register USB0_ENDPT9 8 R W 00h 33 5 17 554 4007_20E8 Endpoint Control register USB0_ENDPT10 8 R W 00h 33 5 17 554 4007_20EC Endpoint Control register USB0_ENDPT11 8 R W 0...

Page 543: ...f 0x04 This value is defined for the USB peripheral Address 4007_2000h base 0h offset 4007_2000h Bit 7 6 5 4 3 2 1 0 Read 0 ID Write Reset 0 0 0 0 0 1 0 0 USBx_PERID field descriptions Field Descripti...

Page 544: ...icates the revision number of the USB Core 33 5 4 Peripheral Additional Info register USBx_ADDINFO Reads back the value of the Host Enable bit Address 4007_2000h base Ch offset 4007_200Ch Bit 7 6 5 4...

Page 545: ...t be disabled 4 SLEEP This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms The sleep timer is reset by activity on the USB bus 3 TOKDNE This bit is set when the current...

Page 546: ...ved This field is reserved This read only field is reserved and always has the value 0 5 RESUMEEN RESUME Interrupt Enable 0 Disables the RESUME interrupt 1 Enables the RESUME interrupt 4 SLEEPEN SLEEP...

Page 547: ...RX transfer this would cause a receive data overflow condition This interrupt is useful when developing device arbitration hardware for the microprocessor and the USB module to minimize bus request an...

Page 548: ...Enable 0 Disables the BTSERR interrupt 1 Enables the BTSERR interrupt 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 DMAERREN DMAERR Interrupt Enable 0...

Page 549: ...t in the ISTAT register causes the SIE to update STAT with the contents of the next STAT value If the data in the STAT holding register is valid the SIE immediately reasserts to TOKDNE interrupt Addre...

Page 550: ...it allows the SIE to continue token processing This bit is set by the SIE when a SETUP Token is received allowing software to dequeue any pending packet transactions in the BDT before resuming token p...

Page 551: ...eserved This field is reserved This read only field is reserved and always has the value 0 ADDR USB Address Defines the USB address that the USB module decodes in peripheral mode 33 5 12 BDT Page regi...

Page 552: ...re used to compute the address where the current Buffer Descriptor Table BDT resides in system memory 33 5 14 Frame Number register High USBx_FRMNUMH The Frame Number registers low and high contain th...

Page 553: ...ptor Table resides in system memory 33 5 16 BDT Page Register 3 USBx_BDTPAGE3 Contains an 8 bit value used to compute the address where the current Buffer Descriptor Table BDT resides in system memory...

Page 554: ...nable Endpoint for RX and TX as well as control SETUP transfers Address 4007_2000h base C0h offset 4d i where i 0d to 15d Bit 7 6 5 4 3 2 1 0 Read 0 EPCTLDIS EPRXEN EPTXEN EPSTALL EPHSHK Write Reset 0...

Page 555: ...into the suspend state 0 USB transceiver is not in suspend state 1 USB transceiver is in suspend state 6 PDE Enables the weak pulldowns on the USB transceiver 0 Weak pulldowns are disabled on D and D...

Page 556: ...reserved This read only field is reserved and always has the value 0 33 5 20 USB OTG Control register USBx_CONTROL Address 4007_2000h base 108h offset 4007_2108h Bit 7 6 5 4 Read 0 DPPULLUPNONOTG Writ...

Page 557: ...oftware must set this bit to 1b 5 USBRESMEN Asynchronous Resume Interrupt Enable This bit when set allows the USB module to send an asynchronous wakeup event to the MCU upon detection of resume signal...

Page 558: ...nchronous interrupt 33 5 22 Frame Adjust Register USBx_USBFRMADJUST Address 4007_2000h base 114h offset 4007_2114h Bit 7 6 5 4 3 2 1 0 Read ADJ Write Reset 0 0 0 0 0 0 0 0 USBx_USBFRMADJUST field desc...

Page 559: ...time rough to track transition default 1 Go back to rough stage whenever bus reset or bus resume occurs 5 RESTART_ IFRTRIM_EN Restart from IFR trim value IRC48 has a default trim fine value whose def...

Page 560: ...C48M module 0 Reserved This field is reserved 33 5 25 Clock recovery combined interrupt enable USBx_CLK_RECOVER_INT_EN Enables or masks the individual interrupt flags which are logically OR ed togethe...

Page 561: ...Write w1c w1c w1c Reset 0 0 0 0 0 0 0 0 USBx_CLK_RECOVER_INT_STATUS field descriptions Field Description 7 5 Reserved This field is reserved Should always be written as 0 4 OVF_ERROR Indicates that t...

Page 562: ...s the HIRC 48mhz clock by setting SIM_SOPT2 USBSRC 1b 4 The USB clock source can be selected from the USB_CLKIN pad by setting SIM_SOPT2 USBSRC 0b For chip specific details see the USB FS OTG controll...

Page 563: ...r supply is below 3 6 V the regulator goes to pass through mode The following figure shows the ideal relation between the regulator output and input power supply OUTPUT Volt 3 3 2 1 2 7 3 6 5 5 INPUT...

Page 564: ...ANDBY regulator output is connected to the external pin Internal power mode signals control whether the module is in RUN or STANDBY mode 34 1 2 Features Low drop out linear voltage regulator with one...

Page 565: ...cting the STANDBY regulator output to the external pin is closed SHUTDOWN The module is disabled The regulator is enabled by default This means that once the power supply is provided the module power...

Page 566: ...USB Voltage Regulator Module Signal Descriptions KL27 Sub Family Reference Manual Rev 5 01 2016 566 Freescale Semiconductor Inc...

Page 567: ...in Master Mode Bus 2 SPI1 operates at maximum configurable speed 24MHz in Master Mode System clock 2 The following registers are not available in this device Table 35 1 SPI register Absolute address R...

Page 568: ...feature decreases CPU loading allowing CPU time to be used for other work 35 2 1 Features The SPI includes these distinctive features Master mode or slave mode operation Full duplex or single wire bid...

Page 569: ...progress stops but is resumed after the CPU enters run mode If the SPI is configured as a slave reception and transmission of a data continues so that the slave stays synchronized to the master The S...

Page 570: ...gister at the start of a data transfer After shifting in 8 bits or 16 bits as determined by the SPIMODE bit of data the data is transferred into the double buffered receiver where it can be read from...

Page 571: ...TY SHIFT IN Tx BUFFER WRITE DH DL SPI SHIFT REGISTER Rx BUFFER READ DH DL PIN CONTROL MASTER CLOCK SLAVE CLOCK BUS RATE CLOCK SPIBR CLOCK GENERATOR MASTER SLAVE MODE SELECT CLOCK LOGIC MODE FAULT DETE...

Page 572: ...E MODFEN SSOE SPC0 BIDIROE IN FIFOMODE Rx FIFO 64 bits deep Tx BUFFER EMPTY Rx BUFFER FULL SHIFT CLOCK Tx FIFO 64 bits deep 8 OR 16 BIT MODE SPIMODE RNFULLF RNFULLIEN TNEAREF TNEARIEN MH ML RX BUFFER...

Page 573: ...0 is 0 not bidirectional mode this pin is the serial data input When the SPI is enabled as a slave and SPC0 is 0 this pin is the serial data output If SPC0 is 1 to select single wire bidirectional mod...

Page 574: ...W 00h 35 4 8 584 4007_600A SPI clear interrupt register SPI0_CI 8 R W 00h 35 4 9 585 4007_600B SPI control register 3 SPI0_C3 8 R W 00h 35 4 10 586 4007_7000 SPI Status Register SPI1_S 8 R 20h 35 4 1...

Page 575: ...ister is set which allows the CPU to start filling the transmit FIFO before it is empty and thus to prevent breaks in SPI transmission NOTE At an initial POR the values of TNEAREF and RFIFOEF are 0 Ho...

Page 576: ...SPTEF is automatically cleared when the DMA transfer for the transmit DMA request is completed TX DMA Done is asserted SPTEF is automatically set when all data from the transmit buffer transfers into...

Page 577: ...data remain in the transmit FIFO provided C3 TNEAREF_MARK is 0 or when only two 16 bit words or four 8 bit bytes of data remain in the transmit FIFO provided C3 TNEAREF_MARK is 1 If FIFOMODE is not en...

Page 578: ...ter may be read or written at any time Address Base address 1h offset Bit 7 6 5 4 3 2 1 0 Read 0 SPPR 2 0 SPR 3 0 Write Reset 0 0 0 0 0 0 0 0 SPIx_BR field descriptions Field Description 7 Reserved Th...

Page 579: ...ption 7 SPMIE SPI Match Interrupt Enable This is the interrupt enable bit for the SPI receive data buffer hardware match SPMF function 0 Interrupts from SPMF inhibited use polling 1 When SPMF is 1 req...

Page 580: ...ed so SPI data I O pin acts as an input 1 SPI I O pin enabled as an output 2 RXDMAE Receive DMA enable This is the enable bit for a receive DMA request When this bit is set to 1 a receive DMA request...

Page 581: ...when FIFOMODE is not present or is 0 or Read FIFO Full Interrupts are enabled when FIFOMODE is 1 6 SPE SPI System Enable Enables the SPI system and dedicates the SPI port pins to SPI system functions...

Page 582: ...SPI In slave mode SS pin function is slave select input When C2 MODFEN is 1 In master mode SS pin function is SS input for mode fault In slave mode SS pin function is slave select input 1 When C2 MODF...

Page 583: ...Reset 0 0 0 0 0 0 0 0 SPIx_MH field descriptions Field Description Bits 15 8 Hardware compare value high byte 35 4 7 SPI Data Register low SPIx_DL This register together with the DH register is both t...

Page 584: ...mode only the DL register is available Reads of the DH register return all zeros Writes to the DH register are ignored In 16 bit mode reading either byte the DH or DL register latches the contents of...

Page 585: ...ags in the status register are reset and entries in the FIFO are flushed with the corresponding error flags set These flags are cleared when the CI register is read while the flags are set Address Bas...

Page 586: ...ransmit and receive buffers It applies only for an instance of the SPI module that supports the FIFO feature FIFO mode is enabled by setting the FIFOMODE bit to 1 A write to this register occurs only...

Page 587: ...s bit selects the mechanism by which the SPRF SPTEF TNEAREF and RNFULLF interrupts are cleared 0 These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIF...

Page 588: ...POL bits in the SPI Control Register 1 SPIx_C1 select one of four possible clock formats to be used by the SPI system The CPOL bit simply selects a non inverted or inverted clock C1 CPHA is used to ac...

Page 589: ...disables the slave output buffer MISO or SISO in bidirectional mode As a result all outputs are disabled and SPSCK MOSI and MISO are inputs If a transmission is in progress when the mode fault occurs...

Page 590: ...shifting of the SPI shift register occurs Although the SPI is capable of duplex operation some SPI peripherals are capable of only receiving SPI data in a slave mode For these simpler devices there i...

Page 591: ...To indicate transfer is complete the SPRF flag in the SPI Status Register is set Note A change of the bits FIFOMODE SPIMODE C2 BIDIROE with C2 SPC0 set C1 CPOL C1 CPHA C1 SSOE C1 LSBFE C2 MODFEN and C...

Page 592: ...ic flow of SPI transmission by DMA is as below Configure SPI before Transmission RESET Configure DMA Controller for SPI Transmission Set TXDMAE RXDMAE 1 to enable Transmit Receive by DMA Set SPE 1 to...

Page 593: ...ntroller to transfer data from memory to the SPI data register The DMA performs a single data transfer per DMA request in cycle steal mode Therefore a single byte word is written to the SPI data regis...

Page 594: ...ites to SPIx_DH and SPIx_MH will be ignored In 16 bit mode SPIMODE 1 the SPI Data Register is comprised of two bytes SPIx_DH and SPIx_DL Reading either byte SPIx_DH or SPIx_DL latches the contents of...

Page 595: ...ting at the first SPSCK edge and bit 8 ending one half SPSCK cycle after the eighth SPSCK edge The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE Both...

Page 596: ...alues on their MISO and MOSI inputs respectively At the third SPSCK edge the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit valu...

Page 597: ...ter The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave The SS OUT waveform applies to the slave select output from a master pr...

Page 598: ...f 1 2 3 4 5 6 7 or 8 The rate select bits SPR3 SPR2 SPR1 SPR0 divide the output of the prescaler stage by 2 4 8 16 32 64 128 256 or 512 to get the internal SPI master mode bit rate clock The baud rate...

Page 599: ...e SPI uses only one serial data pin for the interface with one or more external devices C1 MSTR decides which pin to use The MOSI pin becomes the serial data I O MOMI pin for the master mode and the M...

Page 600: ...and it sets the MODF bit in the SPI status register automatically provided that C2 MODFEN is set In the special case where the SPI is in master mode and C2 MODFEN is cleared the SS pin is not used by...

Page 601: ...a power conservation state when the CPU is in wait mode If C2 SPISWAI is set and the SPI is configured for master any transmission and reception in progress stops at Wait mode entry The transmission a...

Page 602: ...to this type of stop mode the SPI module clock is disabled held high or low If the SPI is in master mode and exchanging data when the CPU enters the Stop mode the transmission is frozen until the CPU...

Page 603: ...vice routine ISR should check the flag bits to determine which event caused the interrupt The service routine should also clear the flag bit s before returning from the ISR usually near the beginning...

Page 604: ...occurs when the data in the receive data buffer is equal to the data in the SPI Match Register In 8 bit mode SPMF is set only after bits 7 0 in the receive data buffer are determined to be equivalent...

Page 605: ...peripheral bus clock is stopped but internal logic states are retained 3 The SPI module is in slave mode 4 The received transmission ends 5 When the FIFO feature is supported FIFO mode is disabled C3...

Page 606: ...is set up for master mode with only hardware match interrupts enabled The SPI runs in 16 bit mode at a maximum baud rate of SPI module clock divided by 2 Clock phase and polarity are set for an activ...

Page 607: ...g for master mode Bit 3 0 RNFULLF TNEARF TXFULLF and RFIFOEF 0 Reserved when FIFOMODE is not present or is 0 or FIFO flags when FIFOMODE is 1 Bit 3 0 0 FIFOMODE is not enabled SPIx_MH 0xXX In 16 bit m...

Page 608: ...F 1 SPTEF 1 INITIALIZE SPI SPIxC1 0x54 SPIxC2 SPIxBR 0x00 0xC0 SPIxMH 0xXX SPIxDH SPIxDL SPIxDH SPIxDL Figure 35 10 Initialization Flowchart Example for SPI Master Device in 16 bit Mode for FIFOMODE 0...

Page 609: ...OMODE TXFULLF 1 RNFULLF 1 SPRF 1 RFIFOEF 1 SPIxDH SPIxDL SPIxDH SPIxDL SPIxMH 0xXX Figure 35 11 Initialization Flowchart Example for SPI Master Device in 16 bit Mode for FIFOMODE 1 Chapter 35 Serial P...

Page 610: ...Initialization application information KL27 Sub Family Reference Manual Rev 5 01 2016 610 Freescale Semiconductor Inc...

Page 611: ...r implemented in the IICx module controlled by the I2Cx_FLT FLT registers is clocked from the core system clock and thus has filter granularity in core system clock cycle counts NOTE For I2C instance...

Page 612: ...etection Bus busy detection General call recognition 10 bit address extension Support for System Management Bus SMBus Specification version 2 Programmable input glitch filter Low power mode wakeup on...

Page 613: ...n Out Data Shift Register Address Compare Figure 36 1 I2C Functional block diagram 36 3 I2C signal descriptions The signal properties of I2C are shown in the table found here Table 36 1 I2C signal des...

Page 614: ...36 4 11 625 4006_600B I2C SCL Low Timeout Register Low I2C0_SLTL 8 R W 00h 36 4 12 626 4006_600C I2C Status register 2 I2C0_S2 8 R W 01h 36 4 13 626 4006_7000 I2C Address Register 1 I2C1_A1 8 R W 00h...

Page 615: ...2 1 0 Read MULT ICR Write Reset 0 0 0 0 0 0 0 0 I2Cx_F field descriptions Field Description 7 6 MULT Multiplier Factor Defines the multiplier factor mul This factor is used along with the SCL divider...

Page 616: ...e For example if the I2C module clock speed is 8 MHz the following table shows the possible hold time values with different ICR and MULT selections to achieve an I2C baud rate of 100 kbit s MULT ICR H...

Page 617: ...f FACK is cleared or the current receiving byte if FACK is set 1 No acknowledge signal is sent to the bus on the following receiving data byte if FACK is cleared or the current receiving data byte if...

Page 618: ...ransmit mode NOTE In the buffer mode TCF is cleared automatically by internal reading or writing the data register I2C_D with no need waiting for manually reading writing the I2C data register in Rx T...

Page 619: ...reading from slave 1 IICIF Interrupt Flag This bit sets when an interrupt is pending This bit must be cleared by software by writing 1 to it such as in the interrupt routine One of the following even...

Page 620: ...f transfer in master and slave modes for the transmission to begin For example if the I2C module is configured for master transmit but a master receive is desired reading the Data register does not in...

Page 621: ...MEN Range Address Matching Enable This bit controls the slave address matching for addresses between the values of the A1 and RA registers When this bit is set a slave address matching occurs for any...

Page 622: ...1 s IICIE bit was set to 1 before the MCU entered stop mode system software will receive the interrupt triggered by the I2C Status Register s TCF bit after the MCU wakes from the stop mode 0 Stop hol...

Page 623: ...to 1 any nonzero value write enables this register This register value can be considered as a maximum boundary in the range matching mode 0 Reserved This field is reserved This read only field is res...

Page 624: ...N Second I2C Address Enable Enables or disables SMBus device default address 0 I2C address register 2 matching is disabled 1 I2C address register 2 matching is enabled 4 TCKSEL Timeout Counter Clock S...

Page 625: ...Write Reset 1 1 0 0 0 0 1 0 I2Cx_A2 field descriptions Field Description 7 1 SAD SMBus Address Contains the slave address used by the SMBus This field is used on the device default address or other re...

Page 626: ...d is reserved and always has the value 0 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 Reserved This field is reserved This read only field is reserve...

Page 627: ...serial data line SDA and a serial clock line SCL for data transfers All devices connected to it must have open drain or open collector outputs A logic AND function is exercised on both lines with ext...

Page 628: ...d as a high to low transition of SDA while SCL is high This signal denotes the beginning of a new data transfer each data transfer might contain several bytes of data and brings all slaves out of thei...

Page 629: ...ch data byte is followed by a ninth acknowledge bit which is signaled from the receiving device by pulling SDA low at the ninth clock In summary one complete data transfer needs nine clock pulses If t...

Page 630: ...ave receive mode and stop driving SDA output In this case the transition from master to slave mode does not generate a STOP condition Meanwhile hardware sets a status bit to indicate the loss of arbit...

Page 631: ...can drive SCL low for the required period and then release it If the slave s SCL low period is greater than the master s SCL low period the resulting SCL bus signal s low period is stretched In other...

Page 632: ...2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32...

Page 633: ...110 AD10 AD9 R W 0 A1 Slave address second byte AD 8 1 A2 Data A Data A A P After the master transmitter has sent the first byte of the 10 bit address the slave receiver sees an I2C interrupt User sof...

Page 634: ...matching process It provides a 7 bit address If the ADEXT bit is set AD 10 8 in Control Register 2 participates in the address matching process It extends the I2C primary slave address to a 10 bit ad...

Page 635: ...ble to receive a new START condition within the timeframe of TTIMEOUT MAX SMBus defines a clock low timeout TTIMEOUT of 35 ms specifies TLOW SEXT as the cumulative clock low extend time for a slave de...

Page 636: ...e timeout intervals TLOW SEXT and TLOW MEXT When in master mode the I2C module must not cumulatively extend its clock cycles for a period greater than TLOW MEXT within a byte where each byte is define...

Page 637: ...edge its own address as a mechanism to detect the presence of a removable device such as a battery or docking station on the bus In addition to indicating a slave device busy condition SMBus uses the...

Page 638: ...ss IAAS IICIF IICIE Arbitration lost ARBL IICIF IICIE I2C bus stop detection STOPF IICIF IICIE SSIE I2C bus start detection STARTF IICIF IICIE SSIE SMBus SCL low timeout SLTF IICIF IICIE SMBus SCL hig...

Page 639: ...ters try to control the bus at the same time the relative priority of the contending masters is determined by a data arbitration procedure The I2C module asserts the arbitration lost interrupt when it...

Page 640: ...or the I2C module The width of the glitch to absorb can be specified in terms of the number of half I2C module clock cycles A single Programmable Input Glitch Filter control register is provided Effec...

Page 641: ...tering the next low power mode Address Write must be sent to change the SRW status 36 5 9 DMA support If the DMAEN bit is cleared and the IICIE bit is set an interrupt condition generates an interrupt...

Page 642: ...when the baud rate is very slow To write twice in one frame during the next to last ISR do a dummy read from the I2C_D buffer at Tx side or the TCF will stay high because the TCF is cleared by write r...

Page 643: ...smit data 4 Initialize RAM variables used to achieve the routine shown in the following figure 5 Write Control Register 1 to enable TX 6 Write Control Register 1 to enable MST master mode 7 Write Data...

Page 644: ...es 1 If general call is enabled check to determine if the received address is a general call address 0x00 If the received address is a general call address the general call must be handled by user sof...

Page 645: ...Clear IICIF Notes 1 If general call or SIICAEN is enabled check to determine if the received address is a general call address 0x00 or an SMBus device default address In either case they must be handl...

Page 646: ...Initialization application information KL27 Sub Family Reference Manual Rev 5 01 2016 646 Freescale Semiconductor Inc...

Page 647: ...nabled 37 2 Introduction 37 2 1 Features Features of the LPUART module include Full duplex standard non return to zero NRZ format Programmable baud rates 13 bit modulo divider with configurable oversa...

Page 648: ...tional 13 bit break character generation 11 bit break character detection Configurable idle length detection supporting 1 2 4 8 16 32 64 or 128 idle characters Selectable transmitter output and receiv...

Page 649: ...tristated in single wire mode whenever the transmitter is disabled or transmit direction is configured for receive data I O LPUART_RX Receive data I 37 2 4 Block diagram The following figure shows the...

Page 650: ...TxD Direction TO TxD Pin Logic Loop Control To Receive Data In To TxD Pin Tx Interrupt Request LOOPS RSRC TIE TC TDRE M PT PE TCIE TE SBK T8 TXDIR Load From LPUARTx_D TXINV BRK13 ASYNCH MODULE CLOCK...

Page 651: ...LPUART Baud Rate Register LPUART0_BAUD 32 R W 0F00_0004h 37 3 1 652 4005_4004 LPUART Status Register LPUART0_STAT 32 R W 00C0_0000h 37 3 2 654 4005_4008 LPUART Control Register LPUART0_CTRL 32 R W 000...

Page 652: ...of the serial transmission This bit should only be changed when the transmitter and receiver are both disabled 0 Receiver and transmitter use 8 bit or 9 bit data characters 1 Receiver and transmitter...

Page 653: ...ng edge of the baud rate clock 16 RESYNCDIS Resynchronization Disable When set disables the resynchronization of the received data word when a data one followed by data zero transition is detected Thi...

Page 654: ...ss 4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R LBKDIF RXEDGIF MSBF RXINV RWUID BRK13 LBKDE RAF TDRE TC RDRF IDLE OR NF FE PF W w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 1 1...

Page 655: ...ceive data inverted 27 RWUID Receive Wake Up Idle Detect For RWU on idle character RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit For address match wakeup RWUID...

Page 656: ...LPUART_CTRL SBK 0 Transmitter active sending data a preamble or a break 1 Transmitter idle transmission activity complete 21 RDRF Receive Data Register Full Flag RDRF is set when the receive buffer LP...

Page 657: ...LPUART_DATA was received with noise detected within the character To clear NF write logic one to the NF 0 No noise detected 1 Noise detected in the received character in LPUART_DATA 17 FE Framing Erro...

Page 658: ...10 bit data formats When reading 9 bit or 10 bit data read R8 before reading LPUART_DATA T9 is the tenth data bit received when the LPUART is configured for 10 bit data formats When writing 10 bit da...

Page 659: ...Interrupt Enable This bit enables the noise flag NF to generate hardware interrupt requests 0 NF interrupts disabled use polling 1 Hardware interrupt requested when NF is set 25 FEIE Framing Error In...

Page 660: ...y state RWU automatically clears when an RWU event occurs that is an IDLE event when CTRL WAKE is clear or an address match when CTRL WAKE is set with STAT RWUID is clear NOTE RWU must be set only wit...

Page 661: ...where transmitter outputs are internally connected to receiver input see RSRC bit 6 DOZEEN Doze Enable 0 LPUART is enabled in Doze mode 1 LPUART is disabled in Doze mode 5 RSRC Receiver Source Select...

Page 662: ...ILT 1 a logic 0 is automatically shifted after a received stop bit therefore resetting the idle count 0 Idle character bit count starts after start bit 1 Idle character bit count starts after stop bi...

Page 663: ...ARITYE FRETSC RXEMPT IDLINE 0 R9T9 R8T8 R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 W Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 LPUARTx_DATA field descriptions Field Description 31 16 Reserved This field is r...

Page 664: ...not valid 11 IDLINE Idle Line Indicates the receiver line was idle before receiving the character in DATA 9 0 Unlike the IDLE flag this bit can set for the first character received when the receiver...

Page 665: ...input data addresses when the most significant bit is set and the associated BAUD MAEN bit is set If a match occurs the following data is transferred to the data register If a match fails the followi...

Page 666: ...mitter output is inverted by setting CTRL TXINV The transmitter is enabled by setting the CTRL TE bit This queues a preamble character that is one full character frame of the idle state The transmitte...

Page 667: ...eescale Semiconductor LPUART the break characters are received as 0s in all data bits and a framing error LPUART_STAT FE 1 occurs A break character can also be transmitted by writing to the LPUART_DAT...

Page 668: ...art bit of logic 0 eight to ten data bits msb or lsb first and one or two stop bits of logic 1 For information about 9 bit or 10 bit data mode refer to 8 bit 9 bit and 10 bit data modes For the remain...

Page 669: ...he logic level is interpreted to be that of the majority of the samples taken during the bit time If any sample in any bit time including the start and stop bits in a character frame fails to agree wi...

Page 670: ...rs wake up in time to look at the first character s of the next message During receiver address matching the address matching is performed in hardware and the LPUART receiver will ignore all character...

Page 671: ...rol bit selects one of two ways to detect an idle line When LPUART_CTRL ILT is cleared the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count...

Page 672: ...all following characters with logic zero in the bit position immediately preceding the stop bit are also discarded If both the LPUART_BAUD MAEN1 and LPUART_BAUD MAEN2 bits are negated the receiver ope...

Page 673: ...3 2 6 Match On Match Off operation Match on match off operation is enabled when both LPUART_BAUD MAEN1 and LPUART_BAUD MAEN2 are set and LPUART_BAUD MATCFG is equal to 10 In this function a character...

Page 674: ...is copied at the same time data is transferred from LPUART_DATA 7 0 to the shifter The 9 bit data mode is typically used with parity to allow eight bits of data plus the parity in the ninth bit or it...

Page 675: ...the LPUART_CTRL TXDIR bit controls the direction of serial data on the LPUART_TX pin When LPUART_CTRL TXDIR is cleared the LPUART_TX pin is an input to the receiver and the transmitter is temporarily...

Page 676: ...has received at least one new character and has set LPUART_STAT RDRF If the associated error was detected in the received character that caused LPUART_STAT RDRF to be set the error flags noise flag LP...

Page 677: ...le supports LIN Slave operation 38 2 Introduction The UART allows asynchronous serial communication with peripheral devices and CPUs 38 2 1 Features The UART includes the following features Full duple...

Page 678: ...ion of NACK d packets with programmable retry threshold Support for 11 and 12 ETU transfers Detection of initial packet and automated transfer parameter programming Interrupt driven operation with sev...

Page 679: ...p mode The UART is inactive during Stop mode for reduced power consumption The STOP instruction does not affect the UART register states but the UART module clock is disabled The UART operation resume...

Page 680: ...rate TXD O Transmit data Serial data output from transmitter State meaning Whether TXD is interpreted as a 1 or 0 depends on the bit encoding method along with other configuration settings Timing Driv...

Page 681: ...38 4 14 697 4006_C01A UART 7816 Interrupt Status Register UART2_IS7816 8 R W 00h 38 4 15 699 4006_C01B UART 7816 Wait Parameter Register UART2_WP7816 8 R W 00h 38 4 16 701 4006_C01C UART 7816 Wait N...

Page 682: ...6_C000h base 0h offset 4006_C000h Bit 7 6 5 4 3 2 1 0 Read Reserved RXEDGIE 0 SBR Write Reset 0 0 0 0 0 0 0 0 UARTx_BDH field descriptions Field Description 7 Reserved Reserved This field is reserved...

Page 683: ...tails NOTE The baud rate generator is disabled until C2 TE or C2 RE is set for the first time after reset The baud rate generator is disabled when SBR 0 Writing to BDH has no effect without writing to...

Page 684: ...starts counting logic 1s as idle character bits The count begins either after a valid start bit or after the stop bit If the count begins after the start bit then a string of logic 1s preceding the s...

Page 685: ...DMA transfer requests based on the state of C5 TDMAS NOTE If C2 TIE and C5 TDMAS are both set then TCIE must be cleared and D D must not be written unless servicing a DMA request 0 TDRE interrupt and...

Page 686: ...be determined by S2 RAF If the flag is set to wake up an IDLE event and the channel is already idle it is possible that the UART will discard data This is because the data must be received after an ID...

Page 687: ...ata Register Empty Flag TDRE will set when the transmit data register D is empty To clear TDRE read S1 when TDRE is set and then write to the UART data register D 0 Transmit data buffer is full 1 Tran...

Page 688: ...ffer even if sufficient room exists Additionally while the OR flag is set the RDRF and IDLE flags are blocked from asserting that is transition from an inactive to an active state To clear OR read S1...

Page 689: ...escription NOTE The active edge is detected only in two wire mode and on receiving data coming from the RxD pin 0 No active edge on the receive pin has occurred 1 An active edge on the receive pin has...

Page 690: ...ansmit break character is 10 11 or 12 bits long or 13 or 14 bits long See for the length of the break character for the different configurations The detection of a framing error is not affected by thi...

Page 691: ...nt only to the single wire mode When C7816 ISO7816E is set enabled and C7816 TTYPE 1 this field is automatically cleared after the requested block is transmitted This condition is detected when TL7816...

Page 692: ...bled 1 PF interrupt requests are enabled 38 4 8 UART Data Register UARTx_D This register is actually two separate registers Reads return the contents of the read only receive data register and writes...

Page 693: ...gister 38 4 9 UART Match Address Registers 1 UARTx_MA1 The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4 MAEN field is set If a...

Page 694: ...0 All data received is transferred to the data buffer if MAEN2 is cleared 1 All data received with the most significant bit cleared is discarded All data received with the most significant bit set is...

Page 695: ...a register empty flag S1 TDRE to generate interrupt or DMA requests if C2 TIE is set NOTE If C2 TIE is cleared TDRE DMA and TDRE interrupt request signals are not asserted when the TDRE flag is set re...

Page 696: ...d This field is reserved This read only field is reserved and always has the value 0 4 ONACK Generate NACK on Overflow When this field is set the receiver automatically generates a NACK response if a...

Page 697: ...ial character 1 Receiver searches for initial character 1 TTYPE Transfer Type Indicates the transfer protocol being used See ISO 7816 smartcard support for more details 0 T 0 per the ISO 7816 specific...

Page 698: ...ertion of IS7816 INITD results in the generation of an interrupt 3 ADTE ATR Duration Timer Interrupt Enable 0 The assertion of IS7816 ADT does not result in the generation of an interrupt 1 The assert...

Page 699: ...and the leading edge of the next response character has exceeded the programmed value This flag asserts only when C7816 TTYPE 0 This interrupt is cleared by writing 1 0 Wait time WT has not been viola...

Page 700: ...a NACK the internal NACK detection counter is cleared and the count restarts from zero on the next received NACK This interrupt is cleared by writing 1 0 The number of retries and corresponding NACKS...

Page 701: ...TYPE 1 See Wait time and guard time parameters 38 4 17 UART 7816 Wait N Register UARTx_WN7816 The WN7816 register contains a parameter that is used in the calculation of the guard time counter This re...

Page 702: ...egister must be written to only when C7816 ISO_7816E is not set Address 4006_C000h base 1Eh offset 4006_C01Eh Bit 7 6 5 4 3 2 1 0 Read TXTHRESHOLD RXTHRESHOLD Write Reset 0 0 0 0 0 0 0 0 UARTx_ET7816...

Page 703: ...0 0 0 0 0 0 0 UARTx_TL7816 field descriptions Field Description TLEN Transmit Length This value plus four indicates the number of characters contained in the block being transmitted This register is a...

Page 704: ...used only when C7816 TTYPE 0 See ATR Duration Time Counter 38 4 22 UART 7816 ATR Duration Timer Register B UARTx_AP7816B_T0 The AP7816B_T0 register contains variables used in the generation of the ATR...

Page 705: ...0 0 0 0 0 0 0 0 UARTx_WP7816A_T0 field descriptions Field Description WI_H Wait Time Integer High C7816 TTYPE 0 Used to calculate the value used for the WT counter This register field provides the mo...

Page 706: ...Bit 7 6 5 4 3 2 1 0 Read WI_L Write Reset 0 0 0 1 0 1 0 0 UARTx_WP7816B_T0 field descriptions Field Description WI_L Wait Time Integer Low C7816 TTYPE 0 Used to calculate the value used for the WT cou...

Page 707: ...0 0 0 0 1 1 0 UARTx_WGP7816_T1 field descriptions Field Description 7 4 CWI1 Character Wait Time Integer 1 C7816 TTYPE 1 Used to calculate the value used for the CWT counter It represents a value betw...

Page 708: ...guard time parameters 38 5 Functional description This section provides a complete functional description of the UART block The UART allows full duplex asynchronous NRZ serial communication between th...

Page 709: ...MA Requests IRQ Requests TxD LOOP CONTROL LOOPS RSRC UART DATA REGISTER UART_D Figure 38 1 Transmitter Block Diagram 38 5 1 1 Transmitter character length The UART transmitter can accommodate either 8...

Page 710: ...s empty The transmit driver routine may respond to this flag by writing additional datawords to the transmit buffer using C3 T8 D as space permits See Application information for specific programing s...

Page 711: ...d at the completion of the current frame Following this the transmit data out signal enters the idle state even if there is data pending in the UART transmit data buffer 38 5 1 4 Transmitting break ch...

Page 712: ...being transmitted the data I O line is in an inactive state If C2 TE is cleared during a transmission the transmit data output signal becomes idle after completion of the transmission in progress Cle...

Page 713: ...nd C4 M10 determine the length of data characters When receiving 9 or 10 bit data C3 R8 is the ninth bit bit 8 38 5 2 2 Receiver bit ordering When S2 MSBF is set the receiver operates such that the fi...

Page 714: ...d initial character the data is not transferred from the receive shift register to the receive buffer Instead the data is overwritten by the next incoming data When the C7816 ISO_7816E is set enabled...

Page 715: ...ion samples Table 38 4 Start bit verification RT3 RT5 and RT7 samples RT8 RT9 RT10 samples when 7816E Start bit verification Noise flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No...

Page 716: ...bit samples In the event that C7816 ISO_7816E is set enabled and C7816 TTYPE 0 verification of a stop bit does not take place Rather starting with RT8 the receiver transmits a NACK as programmed until...

Page 717: ...CK RT CLOCK COUNT RESET RT CLOCK 1 1 1 0 1 0 0 0 PERCEIVED START BIT ACTUAL START BIT LSB RT1 RT1 RT1 RT1 RT1 RT2 RT1 RT3 RT4 RT5 RT6 RT7 RT13 RT12 RT11 RT14 RT1 RT2 RT3 RT4 RT5 RT6 RT7 1 1 0 0 RT10 R...

Page 718: ...CLOCK COUNT RESET RT CLOCK 1 1 1 1 0 PERCEIVED AND ACTUAL START BIT LSB RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT2 RT3 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 1 1 1 1 1...

Page 719: ...RT10 were high SAMPLES Rx pin input RT CLOCK RT CLOCK COUNT RESET RT CLOCK 1 1 1 1 0 0 START BIT LSB RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT10 RT1 RT2 RT3 1 1 1 1 1 0 0 1 0 1 RT4 RT5 RT6 RT...

Page 720: ...ng device may be operating at a baud rate below or above the receiver baud rate Accumulated bit time misalignment can cause one of the three stop bit data samples RT8 RT9 and RT10 to fall outside the...

Page 721: ...ver 170 RT cycles 10 bit times 16 RT cycles 10 RT cycles With the misaligned character shown in the Figure 38 10 the receiver counts 170 RT cycles at the point when the count of the transmitting devic...

Page 722: ...5 2 8 Receiver wakeup C1 WAKE determines how the UART is brought out of the standby state to process an incoming message C1 WAKE enables either idle line wakeup or address mark wakeup Receiver wakeup...

Page 723: ...on is enabled i e C4 MAEN1 or C4 MAEN2 is set then received frame is transferred to receive buffer only if the comparison matches Address mark wakeup allows messages to contain idle characters but req...

Page 724: ...ronized with the module clock and drives the receiver The fractional fine adjust counter adds fractional delays to the baud rate clock to allow fine trimming of the baud rate to match the system baud...

Page 725: ...795 00000 0 1760 1 110 0 110 0 00 Table 38 9 Baud rate fine adjust BRFA Baud Rate Fractional Divisor BRFD 0 0 0 0 0 0 32 0 0 0 0 0 1 1 32 0 03125 0 0 0 1 0 2 32 0 0625 0 0 0 1 1 3 32 0 09375 0 0 1 0 0...

Page 726: ...racters that is eight bits are memory mapped in D A frame with eight data bits has a total of 10 bits The most significant bit of the eight data bits can be used as an address mark to wake the receive...

Page 727: ...the internally generated parity bit The ninth bit can either be used as an address mark or a ninth data bit See the following table Table 38 11 Configuration of 9 bit data formats C1 PE UC1 M C1 M10...

Page 728: ...bits of data with MSB first and parity 38 5 4 3 3 Nine bit format with parity disabled The most significant bit can be used for address mark wakeup BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT...

Page 729: ...XD pin for both receiving and transmitting RXD Tx pin input Tx pin output TXINV TRANSMITTER RECEIVER RXINV Figure 38 22 Single wire operation C1 LOOPS 1 C1 RSRC 1 Enable single wire operation by setti...

Page 730: ...convention and inverse convention data formats A variety of interrupts specific to 7816 are provided in addition to the general interrupts to assist software Additionally the module is able to provide...

Page 731: ...n 3F 1 1 1 LHHL HHH LLH direct convention 3B 0 0 0 S2 MSBF C3 TXINV and S2 RXINV must be reset to their default values before C7816 INIT is set Once C7816 INIT is set the receiver searches all receive...

Page 732: ...his mode 38 5 7 3 Protocol T 1 When T 1 protocol is selected the NACK error detection scheme is not used Rather the parity bit is used on a character basis and a CRC or LRC is used on the block basis...

Page 733: ...n the leading edge of two characters within the same block Block wait time BWT is defined as the maximum time between the leading edge character of the last block received by the smartcard device and...

Page 734: ...e is atleast 12 Values smaller than 12 are invalid and will lead to unexpected CWT interrupts The 16 bit Wait Time integer WI is formed by concatenation of WP7816A_T0 WI_H WP7816B_T0 WI_L The 16 bit B...

Page 735: ...nd is not seen by the smartcard device The transmitter clocks operates at 1 16 the frequency of the receive clock so that the receiver is able to sample the received value 16 times during the ETU 38 5...

Page 736: ...s detected on the RxD pin Therefore the active edge can be detected only when in two wire mode A RXEDGIF interrupt is generated only when S2 RXEDGIF is set If RXEDGIE is not enabled before S2 RXEDGIF...

Page 737: ...o assert a DMA transfer request In the receiver S1 RDRF can be configured to assert a DMA transfer request The following table shows the configuration field settings required to configure each flag fo...

Page 738: ...BDL and C4 registers should be programmed such that the transmission frequency provided to the smartcard device must be 1 372th of the clock and must not exceed 5 MHz 2 Write to C1 to configure word l...

Page 739: ...ransmitted until the next receiver transmit switchover is loaded into the transmit buffer 38 9 1 2 Transmission procedure for C7816 TTYPE 1 When the protocol selected is C7816 TTYPE 1 data is transfer...

Page 740: ...pt b If the TDRE flag is set or there is space in the transmit buffer write the data to be transmitted to C3 T8 D A new transmission will not result until data exists in the transmit buffer 3 Repeat s...

Page 741: ...om the receive data buffer This could be done by reading data from the data buffer and processing it 2 Clear S1 OR Note that in some applications if an overrun event is responded to fast enough the lo...

Page 742: ...t will reassert For example consider the following scenario 1 IS7816 WT is programmed to assert after 9600 cycles of unresponsiveness 2 The 9600 cycles pass without a response resulting in the WT inte...

Page 743: ...re used 3 While documentation indicated otherwise in some cases it was possible for S1 IDLE to assert even if S1 OR was set 4 Previously when C2 RWU was set and WAKE 0 the IDLE flag could reassert up...

Page 744: ...Application information KL27 Sub Family Reference Manual Rev 5 01 2016 744 Freescale Semiconductor Inc...

Page 745: ...d by FlexIO_TIMCTLn TRGSEL 4 bit field to use for starting the counter and or reloading the counter The options available are shown in the following table Table 39 1 FlexIO Trigger Options FlexIO_TIMC...

Page 746: ...ble and disable conditions These functions are provided by the FlexIO while adhering to the following key objectives Low software CPU overhead less overhead than software bit banging more overhead tha...

Page 747: ...us operation during stop modes Highly flexible 16 bit timers with support for a variety of internal or external trigger reset enable and disable conditions 39 2 3 Block Diagram The following diagram g...

Page 748: ...in bits Access Reset value Section page 4005_F000 Version ID Register FLEXIO_VERID 32 R 0100_0000h 39 3 1 750 4005_F004 Parameter Register FLEXIO_PARAM 32 R See section 39 3 2 751 4005_F008 FlexIO Co...

Page 749: ...39 3 13 760 4005_F280 Shifter Buffer N Bit Swapped Register FLEXIO_SHIFTBUFBIS0 32 R W 0000_0000h 39 3 14 761 4005_F284 Shifter Buffer N Bit Swapped Register FLEXIO_SHIFTBUFBIS1 32 R W 0000_0000h 39...

Page 750: ...er FLEXIO_TIMCFG2 32 R W 0000_0000h 39 3 18 764 4005_F48C Timer Configuration N Register FLEXIO_TIMCFG3 32 R W 0000_0000h 39 3 18 764 4005_F500 Timer Compare N Register FLEXIO_TIMCMP0 32 R W 0000_0000...

Page 751: ...Parameter Register FLEXIO_PARAM Address 4005_F000h base 4h offset 4005_F004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TRIGGER PIN TIMER SHIFTER W Re...

Page 752: ...FlexIO is enabled in debug modes 29 3 Reserved This field is reserved This read only field is reserved and always has the value 0 2 FASTACC Fast Access Enables fast register accesses to FlexIO regist...

Page 753: ...of the following events occurs For SMOD Receive the status flag is set when SHIFTBUF has been loaded with data from Shifter SHIFTBUF is full and the status flag is cleared when SHIFTBUF register is r...

Page 754: ...value For SMOD Transmit indicates Shifter was ready to load new data from SHIFTBUF before new data had been written into SHIFTBUF SHIFTBUF Underrun For SMOD Match Store indicates a match event occured...

Page 755: ...is set when the 16 bit counter equals zero and decrements this also causes the counter to reload with the value in the compare register 0 Timer Status Flag is clear 1 Timer Status Flag is set 39 3 7 S...

Page 756: ...disabled 1 Shifter Error Flag interrupt enabled 39 3 9 Timer Interrupt Enable Register FLEXIO_TIMIEN Address 4005_F000h base 28h offset 4005_F028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 757: ...0 SSDE Shifter Status DMA Enable Enables DMA request generation when corresponding SSF is set 0 Shifter Status Flag DMA request is disabled 1 Shifter Status Flag DMA request is enabled 39 3 11 Shifter...

Page 758: ...erved This read only field is reserved and always has the value 0 10 8 PINSEL Shifter Pin Select Selects which pin is used by the Shifter input or output 7 PINPOL Shifter Pin Polarity 0 Pin is active...

Page 759: ...Pin 1 Shifter N 1 Output 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 Reserved This field is reserved This read only field is reserved and always ha...

Page 760: ...9 3 13 Shifter Buffer N Register FLEXIO_SHIFTBUFn Address 4005_F000h base 200h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R...

Page 761: ...d Reads return SHIFTBUF 0 31 39 3 15 Shifter Buffer N Byte Swapped Register FLEXIO_SHIFTBUFBYSn Address 4005_F000h base 300h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 762: ...5 SHIFTBUF 0 7 39 3 17 Timer Control N Register FLEXIO_TIMCTLn Address 4005_F000h base 400h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 TRGSEL TRGPOL TRGSRC 0...

Page 763: ...eserved This read only field is reserved and always has the value 0 10 8 PINSEL Timer Pin Select Selects which pin is used by the Timer input or output 7 PINPOL Timer Pin Polarity 0 Pin is active high...

Page 764: ...read only field is reserved and always has the value 0 25 24 TIMOUT Timer Output Configures the initial state of the Timer Output and whether it is affected by the Timer reset 00 Timer output is logic...

Page 765: ...12 TIMDIS Timer Disable Configures the condition that causes the Timer to be disabled and stop decrementing 000 Timer never disabled 001 Timer disabled on Timer N 1 disable 010 Timer disabled on Timer...

Page 766: ...ays has the value 0 39 3 19 Timer Compare N Register FLEXIO_TIMCMPn Address 4005_F000h base 500h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 767: ...timer_store_data timer_shift_pos S FXIO_D0 S FXIO_Dn S synchronizer PINSEL SHIFTERi 1 out INSRC PINPOL PINPOL SHIFTERi out FXIO_D0 FXIO_Dn timer_shift_neg TIMPOL PINSEL PINCFG Figure 39 2 Shifter Micr...

Page 768: ...will clear when the data has been read from the SHIFTBUF register The Shifter Error Flag SHIFTERR SEF and any enabled interrupts will set when an attempt to store data into a full SHIFTBUF register oc...

Page 769: ...rol the loading shifting and storing of the shift registers the counters load the contents of the compare register and decrement down to zero on the FlexIO clock They can perform generic timer functio...

Page 770: ...ft clock after the timer starts decrementing If there is no falling edge on the shift clock before the first rising edge for example when TIMOUT 1 a shifter that is configured to shift on falling edge...

Page 771: ...it will finish A timer enable condition can be detected in the same cycle as a timer disable condition if timer stop bit is disabled or on the first rising edge of the shift clock after the disable c...

Page 772: ...or Shifter Data Input the following synchronization delays occur 1 0 5 1 5 FlexIO clock cycles for external pin 2 1 FlexIO clock cycle for an internally driven pin For timing considerations such as ou...

Page 773: ...tatus flag as inverted internal trigger source Can support CTS by configuring PINSEL 0x1 for Pin 1 and PINPOL 0x1 SHIFTBUFn Data to transmit Transmit data can be written to SHIFTBUF 7 0 to initiate an...

Page 774: ...request Can support MSB first transfer by reading from SHIFTBUFBIS 7 0 register instead The UART Receiver with RTS configuration uses a 2nd Timer to generate the RTS output The RTS will assert when th...

Page 775: ...o Shifters and four Pins Either CPHA 0 or CPHA 1 can be supported and transfers can be supported using the DMA controller For CPHA 1 the select can remain asserted for multiple transfers and the timer...

Page 776: ...Transmit data can be written to SHIFTBUF use the Shifter Status Flag to indicate when data can be written using interrupt or DMA request Can support MSB first transfer by writing to SHIFTBUFBBS regis...

Page 777: ...t or DMA request Can support MSB first transfer by writing to SHIFTBUFBBS register instead SHIFTBUF n 1 Data to receive Received data can be read from SHIFTBUFBYS use the Shifter Status Flag to indica...

Page 778: ...rst transfer by writing to SHIFTBUFBBS register instead SHIFTBUF n 1 Data to receive Received data can be read from SHIFTBUFBYS use the Shifter Status Flag to indicate when data can be read using inte...

Page 779: ...ffer before enabling SCL generation Data transfers can be supported using the DMA controller and the shifter error flag will set on transmit underrun or receive overflow The first timer generates the...

Page 780: ...nabled logic 0 and stop bit enabled logic 1 SHIFTCTLn 0x0101_0082 Configure transmit using Timer 1 on rising edge of clock with inverted output enable open drain output on Pin 0 SHIFTCFG n 1 0x0000_00...

Page 781: ...ger divide of the FlexIO clock frequency and the initial frame sync assertion occurs at the same time as the first bit clock edge The timer uses the start bit to ensure the frame sync is generated one...

Page 782: ...sfer by writing to SHIFTBUF register instead SHIFTBUF n 1 Data to receive Received data can be read from SHIFTBUFBIS use the Shifter Status Flag to indicate when data can be read using interrupt or DM...

Page 783: ...ck as the trigger TIMCMP n 1 0x0000_003F Configure 32 bit transfers Set TIMCMP 15 0 number of bits x 2 1 TIMCFG n 1 0x0020_3500 Configure enable on pin rising edge with trigger high and disable on com...

Page 784: ...Application Information KL27 Sub Family Reference Manual Rev 5 01 2016 784 Freescale Semiconductor Inc...

Page 785: ...imum words per frame 2 Maximum bit clock divider 512 40 1 2 I2S Interrupts The I2S0 has receive and transmit sources of interrupt requests However these sources are OR d together to generate a single...

Page 786: ...ts and DMA requests 40 1 3 4 I2S SAI clock generation Each SAI peripheral can control the input clock selection pin direction and divide ratio of one audio master clock The MCLK Input Clock Select bit...

Page 787: ...outine to enable the module clock before initialization of any of the I2S SAI registers 40 1 4 I2S SAI operation in low power modes 40 1 4 1 Stop and very low power modes In Stop mode the SAI transmit...

Page 788: ...the end of the current frame 40 2 Introduction The I2S or I2S module provides a synchronous audio interface SAI that supports full duplex serial interfaces with frame synchronization such as I2S AC97...

Page 789: ...module operates in these power modes Run mode stop modes low leakage modes and Debug mode 40 2 3 1 Run mode In Run mode the SAI transmitter and receiver operate normally 40 2 3 2 Stop modes In Stop m...

Page 790: ...n TCSR DBGE or RCSR DBGE bit is clear and Debug mode is entered the SAI is disabled after completing the current transmit or receive frame The transmitter and receiver bit clocks are not affected by D...

Page 791: ...I2S0_TCR4 32 R W 0000_0000h 40 4 4 797 4002_F014 SAI Transmit Configuration 5 Register I2S0_TCR5 32 R W 0000_0000h 40 4 5 799 4002_F020 SAI Transmit Data Register I2S0_TDR0 32 W always reads 0 0000_0...

Page 792: ...s the transmitter When software clears this field the transmitter remains enabled and this bit remains set until the end of the current frame 0 Transmitter is disabled 1 Transmitter is enabled or tran...

Page 793: ...g is set 0 No effect 1 FIFO reset 24 SR Software Reset When set resets the internal transmitter logic including the FIFO pointers Software visible registers are not affected except for the status regi...

Page 794: ...r Interrupt Enable Enables disables FIFO error interrupts 0 Disables the interrupt 1 Enables the interrupt 9 FWIE FIFO Warning Interrupt Enable Enables disables FIFO warning interrupts 0 Disables the...

Page 795: ...YNC When the transmitter is configured in synchronous mode the transmitter BCS field and receiver BCS field must be set to the same value When both are set the transmitter and receiver are both clocke...

Page 796: ...active low with drive outputs on falling edge and sample inputs on rising edge 24 BCD Bit Clock Direction Configures the direction of the bit clock 0 Bit clock is generated externally in Slave mode 1...

Page 797: ...Configures which word sets the start of word flag The value written must be one less than the word number For example writing 0 configures the first word in the frame When configured to a value greate...

Page 798: ...d 11 16 bit FIFO packing is enabled 23 17 Reserved This field is reserved This read only field is reserved and always has the value 0 16 FRSZ Frame size Configures the number of words in each frame Th...

Page 799: ...0 FBT 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2Sx_TCR5 field descriptions Field Description 31 29 Reserved This field is reserved This read only field is reserved a...

Page 800: ...16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 W TDR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2Sx_TDRn field descriptions Field Description TDR Transmit Data Register The c...

Page 801: ...n masked 40 4 8 SAI Receive Control Register I2Sx_RCSR Address 4002_F000h base 80h offset 4002_F080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R RE STOPE DBGE BCE 0 0 SR 0 WSF SEF FEF FWF 0...

Page 802: ...this field the receive bit clock remains enabled and this field remains set until the end of the current frame 0 Receive bit clock is disabled 1 Receive bit clock is enabled 27 26 Reserved This field...

Page 803: ...eld is reserved This read only field is reserved and always has the value 0 12 WSIE Word Start Interrupt Enable Enables disables word start interrupts 0 Disables interrupt 1 Enables interrupt 11 SEIE...

Page 804: ...modes of operation When configured for a synchronous mode of operation the transmitter must be configured for asynchronous operation 00 Asynchronous mode 01 Synchronous with transmitter 10 Synchronou...

Page 805: ...nerated bit clock This field has no effect when configured for an externally generated bit clock NOTE Depending on the device some Master Clock options might not be available See the chip specific inf...

Page 806: ...eive operation A channel must be enabled before its FIFO is accessed Changing this field will take effect immediately for generating the FIFO request and warning flags but at the end of each frame for...

Page 807: ...hat caused the FIFO error to set after the FIFO warning flag has been cleared 27 26 Reserved This field is reserved This read only field is reserved and always has the value 0 25 24 FPACK FIFO Packing...

Page 808: ...lways has the value 0 4 MF MSB First Configures whether the LSB or the MSB is received first 0 LSB is received first 1 MSB is received first 3 FSE Frame Sync Early 0 Frame sync asserts with the first...

Page 809: ...ted if there is only one word per frame 15 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 8 FBT First Bit Shifted Configures the bit index for the fi...

Page 810: ...ds in each frame to change from frame to frame Address 4002_F000h base E0h offset 4002_F0E0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RWM W Reset 0...

Page 811: ...signal pin as an output When software clears this field it remains set until the MCLK divider is fully disabled 0 MCLK signal pin is configured as an input that bypasses the MCLK divider 1 MCLK signal...

Page 812: ...nput clock selection pin direction and divide ratio of one audio master clock The input clock selection and pin direction cannot be altered if an SAI module using that audio master clock has been enab...

Page 813: ...the divider input clock frequency The maximum jitter is therefore equal to half the divider input clock period since both edges of the input clock are used in generating the divided clock 40 5 1 2 Bit...

Page 814: ...ware The SAI receiver includes a software reset that resets all receiver internal logic including the bit clock generation status flags and FIFO pointers It does not reset the configuration registers...

Page 815: ...ansmitter for synchronous operation In synchronous mode the transmitter is enabled only when both the receiver and transmitter are both enabled It is recommended that the receiver is the last enabled...

Page 816: ...h to support 8 to 32 bits per word First word length and remaining word lengths can be configured separately Words can be configured to transmit receive MSB first or LSB first These configuration opti...

Page 817: ...e Note that 8 bit writes should only be used when transmitting up to 8 bit data and 16 bit writes should only be used when transmitting up to 16 bit data Writes to a TDR are ignored if the correspondi...

Page 818: ...mit shift register is loaded at the start of each frame and after every second unmasked transmit word The first word transmitted is taken from 16 bit word at byte offset 0 first bit is selected by TCF...

Page 819: ...m stop mode 40 5 7 1 FIFO warning flag The FIFO warning flag is set based on the number of entries in the FIFO The transmit warning flag is set when the number of entries in any of the enabled transmi...

Page 820: ...l continue from the same word number in the frame that caused the FIFO to overflow but only after data has been read from the receive FIFO Software should still clear the RCSR FEF flag but without emp...

Page 821: ...ed by writing to PORTx_PCRn PE All the pins have controllable pull direction using the PORTx_PCRn PS field All the pins default to pullup except for SWD_CLK when enabled 41 1 2 GPIO accessibility in t...

Page 822: ...registers for each port output data register 41 2 1 Features Features of the GPIO module include Port Data Input register visible in all digital pin multiplexing modes Port Data Output register with...

Page 823: ...PORTA31 PORTA0 PORTB31 PORTB0 PORTC31 PORTC0 PORTD31 PORTD0 PORTE31 PORTE0 I O General purpose input output State meaning Asserted The pin is logic 1 Deasserted The pin is logic 0 Timing Assertion Whe...

Page 824: ...ads 0 0000_0000h 41 3 2 826 400F_F048 Port Clear Output Register GPIOB_PCOR 32 W always reads 0 0000_0000h 41 3 3 826 400F_F04C Port Toggle Output Register GPIOB_PTOR 32 W always reads 0 0000_0000h 41...

Page 825: ...s reads 0 0000_0000h 41 3 3 826 400F_F10C Port Toggle Output Register GPIOE_PTOR 32 W always reads 0 0000_0000h 41 3 4 827 400F_F110 Port Data Input Register GPIOE_PDIR 32 R 0000_0000h 41 3 5 827 400F...

Page 826: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PSOR field descriptions Field Description PTSO Port Set Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows...

Page 827: ...iting to this register will update the contents of the corresponding bit in the PDOR as follows 0 Corresponding bit in PDORn does not change 1 Corresponding bit in PDORn is set to the inverse of its e...

Page 828: ...25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PDD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_PDDR field descriptions Field Description PDD P...

Page 829: ...egister bit is set The pin is configured as an output and and the logic state of the pin is equal to the corresponding port data output register To facilitate efficient bit manipulation on the general...

Page 830: ...Functional description KL27 Sub Family Reference Manual Rev 5 01 2016 830 Freescale Semiconductor Inc...

Page 831: ...function is targeted at the manipulation of n bit fields in peripheral registers and is consistent with I O hardware addressing in the Embedded C standard For most BME commands a single core read or...

Page 832: ...agram As shown in the block diagram the BME module interfaces to a crossbar switch AHB slave port as its primary input and sources an AHB bus output to the Peripheral Bridge PBRIDGE controller The BME...

Page 833: ...a crossbar slave AHB system bus port BME responds strictly on the basis of memory addresses for accesses to the peripheral bridge bus controller All functionality associated with the BME module reside...

Page 834: ...onverted into an atomic read modify write that is an indivisible read followed by a write bus sequence Consider decorated store operations first then decorated loads 42 3 1 BME decorated stores The fu...

Page 835: ...translated into a read operation on the output bus using the actual memory address with the decoration removed and then captured in a register 2 Cycle x 1 2nd AHB address phase Write access with the...

Page 836: ...tion and mem_addr 19 0 specifies the address offset into the space based at 0x4000_0000 for peripherals The indicates an address bit don t care The decorated AND write operation is defined in the foll...

Page 837: ...The core performs the required write data lane replication on byte and halfword transfers ioorb 0 0 0 1 mem_addr ioorh 0 0 0 1 mem_addr ioorw 0 0 0 1 mem_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16...

Page 838: ...peration and can be byte 8 bit halfword 16 bit or word 32 bit The core performs the required write data lane replication on byte and halfword transfers ioxorb 0 0 1 mem_addr ioxorh 0 0 1 mem_addr ioxo...

Page 839: ...dth is 16 bits The core performs the required write data lane replication on byte and halfword transfers The BFI operation can be used to insert a single bit into a peripheral For this case the w fiel...

Page 840: ...gister 7 0 xy_z then destination is abxy_zfgh if b 4 and the decorated store strb Rt register 7 0 xyz_ then destination is axyz_efgh if b 5 and the decorated store strb Rt register 7 0 xyz _ then dest...

Page 841: ...the second AHB data phase as the original read data is returned to the processor core For an unsigned bit field extract the decorated load transaction is stalled for one cycle in the BME as the data f...

Page 842: ...bus is translated into a read operation on the output bus with the actual memory address with the decoration removed and then captured in a register 2 Cycle x 1 second AHB address phase Write access...

Page 843: ...xt rdata Figure 42 8 Decorated load unsigned bit field insert timing diagram The decorated unsigned bit field extract follows the same execution template shown in the above figure a 2 cycle read opera...

Page 844: ...e operand returned to the core The data size is specified by the read operation and can be byte 8 bit halfword 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 845: ...filled in the operand returned to the core The data size is specified by the read operation and can be byte 8 bit halfword 16 bit or word 32 bit iolaslb 0 0 1 mem_addr iolaslh 0 0 1 mem_addr iolaslw...

Page 846: ...t justified and zero filled in the operand returned to the core Recall this is the only decorated operation that does not perform a memory write that is UBFX only performs a read The data size is spec...

Page 847: ...y Decode decoration Capture address attributes Idle AHB address phase next BME AHB_dp previous Perform memory read Form bit mask Form rdata mask and capture destination data in register Logically righ...

Page 848: ...erences to peripherals and GPIO based at either 0x4000_F000 or 0x400F_F000 0x5000_0000 0x5FFF_FFFF Decorated BFI UBFX references to peripherals and GPIO only based at 0x4000_F000 42 4 Application info...

Page 849: ...b r2 r3 addr r ADDR wdata r WDATA r2 r3 define IOXORW ADDR WDATA __asm ldr r3 3 26 orr r3 addr mov r2 wdata str r2 r3 addr r ADDR wdata r WDATA r2 r3 define IOXORH ADDR WDATA __asm ldr r3 3 26 orr r3...

Page 850: ...Application information KL27 Sub Family Reference Manual Rev 5 01 2016 850 Freescale Semiconductor Inc...

Page 851: ...RAM controller manages requests from two sources AMBA AHB reads and writes from the system bus program trace packet writes from the processor As part of the MTB functionality there is a DWT Data Watch...

Page 852: ...port from the processor core The private MTB port signals the instruction address information needed for the 64 bit program trace packets written into the system RAM The PRAM controller output interf...

Page 853: ...cond higher addressed word contains the destination of the branch the address it branched to The value stored only records bits 31 1 of the branch address The least significant bit of the value is the...

Page 854: ...to approximately 1600 processor cycles per KB This metric is obviously very sensitive to the runtime characteristics of the user code The MTB_DWT function not shown in the core platform block diagram...

Page 855: ...ropriate crossbar slave port plus the private execution trace bus from the processor core The signals in the private execution trace bus are detailed in the following table taken from the ARM CoreSigh...

Page 856: ...tions Attempting to access these locations can result in UNPREDICTABLE behavior The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN reset values are not programmed prior to enabling...

Page 857: ...32 R See section 43 3 1 14 868 F000_0FD4 Peripheral ID Register MTB_PERIPHID5 32 R See section 43 3 1 14 868 F000_0FD8 Peripheral ID Register MTB_PERIPHID6 32 R See section 43 3 1 14 868 F000_0FDC Pe...

Page 858: ...0 In this configuration the MTB_POSITION register is initialized to 0x2000_0000 0x0000_7FF8 0x0000_00000 Following these two suggested placements provides a full featured circular memory buffer contai...

Page 859: ...are RAZ WI Therefore the active bits in this field are POSITION 14 3 POSITION POINTER 11 0 2 WRAP WRAP This field is set to 1 automatically when the POINTER value wraps as determined by the MTB_MASTE...

Page 860: ...because MTB_FLOW WATERMARK is set then it is not automatically set to 1 if TSTARTEN is 1 and the TSTART input is HIGH In this case tracing can only be restarted if MTB_FLOW WATERMARK or MTB_POSITION P...

Page 861: ...and the MTB_POSITION 14 MASK 3 MTB_POSITION POINTER 11 MASK 1 bits remain unchanged This field causes the trace packet information to be stored in a circular buffer of size 2 MASK 4 bytes that can be...

Page 862: ...ARK field value actions defined by the AUTOHALT and AUTOSTOP bits are performed 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 AUTOHALT AUTOHALT If thi...

Page 863: ...DDR BASEADDR This value is defined with a hardwired signal and the expression 0x2000_0000 RAM_Size 4 For example if the total RAM capacity is 16 KB this field is 0x1FFF_F000 43 3 1 5 Integration Mode...

Page 864: ...00 43 3 1 7 Claim TAG Clear Register MTB_TAGCLEAR The read write Claim Tag Clear Register is used to read the claim status on debug resources A read indicates the claim tag status Writing 1 to a speci...

Page 865: ...ter It is hardwired to specific values used during the auto discovery process by an external debug agent Address F000_0000h base FB4h offset F000_0FB4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 866: ...ly field is reserved and always has the value 0 3 Reserved BIT3 This read only field is reserved and always has the value 1 2 BIT2 BIT2 Connected to NIDEN or DBGEN signal 1 Reserved BIT1 This read onl...

Page 867: ...VICECFG field descriptions Field Description DEVICECFG DEVICECFG Hardwired to 0x0000_0000 43 3 1 13 Device Type Identifier Register MTB_DEVICETYPID This register indicates the device type ID It is har...

Page 868: ...t ID Register MTB_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery process by an external debug agent Address F000_0000h base FF0...

Page 869: ...er MTBDWT_DEVICETYPID 32 R 0000_0004h 43 3 2 8 877 F000_1FD0 Peripheral ID Register MTBDWT_PERIPHID4 32 R See section 43 3 2 9 878 F000_1FD4 Peripheral ID Register MTBDWT_PERIPHID5 32 R See section 43...

Page 870: ...NOCYCCNT 1 cycle counter is not supported MTBDWT_CTRL 24 NOPRFCNT 1 profiling counters are not supported MTBDWT_CTRL 22 CYCEBTENA 0 no POSTCNT underflow packets generated MTBDWT_CTRL 21 FOLDEVTENA 0...

Page 871: ...B_MASTER MASK Address F000_1000h base 24h offset 16d i where i 0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MASK W Reset 0 0 0 0 0 0 0 0 0 0 0...

Page 872: ...it 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 MATCHED 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DATAVADDR0 DATAVSIZE 0 DATAVMATCH 0 FUNCTION W Re...

Page 873: ...ord 10 Word 11 Reserved Any attempts to use this value results in UNPREDICTABLE behavior 9 Reserved This field is reserved This read only field is reserved and always has the value 0 8 DATAVMATCH Data...

Page 874: ...0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FUNCTION W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTBDWT_FCT1 field descriptions Field Description 31 25 Reserved This field is reserv...

Page 875: ...to use this value results in UNPREDICTABLE behavior 43 3 2 6 MTB_DWT Trace Buffer Control Register MTBDWT_TBCTRL The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the actual tr...

Page 876: ...n of MTBDWT_FCT1 MATCHED 1 Trigger TSTART based on the assertion of MTBDWT_FCT1 MATCHED 0 ACOMP0 Action based on Comparator 0 match When the MTBDWT_FCT0 MATCHED is set it indicates MTBDWT_COMP0 addres...

Page 877: ...CECFG DEVICECFG Hardwired to 0x0000_0000 43 3 2 8 Device Type Identifier Register MTBDWT_DEVICETYPID This register indicates the device type ID It is hardwired to specific values used during the auto...

Page 878: ...ent ID Register MTBDWT_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery process by an external debug agent Address F000_1000h bas...

Page 879: ...UID Debug control Data watchpoint unit CoreSight ID Watchpoint control Breakpoint unit CoreSight ID Breakpoint control Optional component Figure 43 3 CoreSight discovery process ROM memory map Absolut...

Page 880: ...ent ID Register ROM_COMPID1 32 R See section 43 3 3 5 882 F000_2FF8 Component ID Register ROM_COMPID2 32 R See section 43 3 3 5 882 F000_2FFC Component ID Register ROM_COMPID3 32 R See section 43 3 3...

Page 881: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROM_TABLEMARK field descriptions Field Description MARK MARK Hardwired to 0x0000_0000 43 3 3 3 System Access Register ROM_SYSACCESS This register indicates system...

Page 882: ...x0000_0008 and all the others to 0x0000_0000 43 3 3 5 Component ID Register ROM_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery...

Page 883: ...bit 16 bit and 32 bit read operations from the program flash memory A write operation to program flash memory results in a bus error In addition the FMC provides two separate mechanisms for accelerati...

Page 884: ...programming model provides control and configuration of the FMC s features For details see the description of the MCM s Platform Control Register PLACR 44 5 Functional description The FMC is a flash...

Page 885: ...example the user may adjust the controls to enable buffering per access type data or instruction NOTE When reconfiguring the FMC do not program the control and configuration inputs to the FMC while th...

Page 886: ...Functional description KL27 Sub Family Reference Manual Rev 5 01 2016 886 Freescale Semiconductor Inc...

Page 887: ...ly the erase operation restores bits from 0 to 1 bits cannot be programmed from a 0 to a 1 CAUTION A flash memory location must be in the erased state before being programmed Cumulative programming of...

Page 888: ...access to one program flash block is possible while programming or erasing data in the other program flash block 45 1 1 2 Other Flash Memory Module Features Internal high voltage supply generator for...

Page 889: ...Command Object A group of flash registers that are used to pass command address data and any associated parameters to the memory controller in the flash memory module Flash block A macro within the fl...

Page 890: ...secutive addresses that can be erased Retention The length of time that data can be kept in the NVM without experiencing errors upon readout Since erased 1 states are subject to degradation just like...

Page 891: ...Registers FPROT0 3 0x0_040F 1 Reserved 0x0_040E 1 Reserved 0x0_040D 1 Flash nonvolatile option byte Refer to the description of the Flash Option Register FOPT 0x0_040C 1 Flash security byte Refer to t...

Page 892: ...the correct order of the individual FCCOB registers is achieved NOTE While a command is running FSTAT CCIF 0 register writes are not accepted to any register except FCNFG and FSTAT The no write rule...

Page 893: ...Flash Common Command Object Registers FTFA_FCCOB9 8 R W 00h 45 3 3 5 898 4002_000F Flash Common Command Object Registers FTFA_FCCOB8 8 R W 00h 45 3 3 5 898 4002_0010 Program Flash Protection Registers...

Page 894: ...Error Flag Indicates an illegal access has occurred to a flash memory resource caused by a violation of the command write sequence or issuing an illegal flash command While ACCERR is set the CCIF flag...

Page 895: ...t enabled An interrupt request is generated whenever the FSTAT CCIF flag is set 6 RDCOLLIE Read Collision Error Interrupt Enable Controls interrupt generation when a flash memory read collision error...

Page 896: ...field is reserved and always has the value 0 45 3 3 3 Flash Security Register FTFA_FSEC This read only register holds all bits associated with the security of the MCU and flash memory module During t...

Page 897: ...SLACC bits is only relevant when SEC is set to secure When SEC is set to unsecure the FSLACC setting does not matter 00 NXP factory access granted 01 NXP factory access denied 10 NXP factory access de...

Page 898: ...B0 FCCOB1 FCCOBB Address 4002_0000h base 4h offset 1d i where i 0d to 11d Bit 7 6 5 4 3 2 1 0 Read CCOBn Write Reset 0 0 0 0 0 0 0 0 FTFA_FCCOBn field descriptions Field Description CCOBn The FCCOB re...

Page 899: ...1 byte the most significant data resides in the lowest FCCOB register number The FCCOB register group may be read and written as individual bytes aligned words 2 bytes or aligned longwords 4 bytes 45...

Page 900: ...gram flash memory that contains the Flash Configuration Field Then reprogram the program flash protection byte Address 4002_0000h base 10h offset 1d i where i 0d to 3d Bit 7 6 5 4 3 2 1 0 Read PROT Wr...

Page 901: ...egister represents 1 32 of the total program flash except for memory configurations with less than 32 KB of program flash where each assigned bit protects 1 KB 0 Program flash region is protected 1 Pr...

Page 902: ...scribed in the application note are available on this device 45 4 2 Interrupts The flash memory module can generate interrupt requests to the MCU upon the occurrence of various flash events These inte...

Page 903: ...he MCU is allowed to enter stop mode CAUTION The MCU should never enter stop mode while any flash command is running CCIF 0 NOTE While the MCU is in very low power modes VLPR VLPW VLPS the flash memor...

Page 904: ...are further discussed in Allowed Simultaneous Flash Operations 45 4 7 Flash Program and Erase All flash functions except read require the user to setup and launch a flash command through a series of...

Page 905: ...arameters have been loaded the user launches the command by clearing FSTAT CCIF by writing a 1 to it FSTAT CCIF remains 0 until the flash command completes The FSTAT register contains a blocking mecha...

Page 906: ...as failure to erase verify may occur during the execution phase Run time errors are reported in FSTAT MGSTAT0 A command may have access errors protection errors and run time errors but the run time er...

Page 907: ...yes no yes Previous command complete no CCIF 1 yes START CCIF 1 Read FSTAT register no yes Bit Polling for Command Completion Check Figure 45 3 Generic flash command write sequence flowchart 45 4 8 2...

Page 908: ...flash sector 0x40 Read 1s All Blocks Verify that all program flash blocks are erased then release MCU security 0x41 Read Once IFR Read 4 bytes of a dedicated 64 byte field in the program flash 0 IFR 0...

Page 909: ...Read 1s Section 0x02 Program Check 0x03 Read Resource 0x06 Program Longword 0x08 Erase Flash Block 0x09 Erase Flash Sector 0x40 Read 1s All Blocks 0x41 Read Once 0x43 Program Once 0x44 Erase All Bloc...

Page 910: ...special cases They can be used during special diagnostic routines to gain confidence that the device is not suffering from the end of life data loss customary of flash memory devices Erased 1 and prog...

Page 911: ...FSTAT ACCERR bit and aborts the command execution if any of the following illegal conditions occur There is an unrecognized command code in the FCCOB FCMD field There is an error in a FCCOB field for...

Page 912: ...sh block Table 45 5 Margin Level Choices for Read 1s Block Read Margin Choice Margin Level Description 0x00 Use the normal read level for 1s 0x01 Apply the User margin to the normal read 1 level 0x02...

Page 913: ...ion operation completes Table 45 8 Margin Level Choices for Read 1s Section Read Margin Choice Margin Level Description 0x00 Use the normal read level for 1s 0x01 Apply the User margin to the normal r...

Page 914: ...set FSTAT CCIF is set after the Program Check operation completes The supplied address must be longword aligned the lowest two bits of the byte address must be 00 Byte 3 data is written to the supplie...

Page 915: ...elect code as shown in Table 45 14 Table 45 13 Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents 7 0 0 0x03 RDRSRC 1 Flash address 23 16 2 Flash address 15 8 3 Flash address 7 0 1 R...

Page 916: ...d FSTAT ACCERR 45 4 10 5 Program Longword Command The Program Longword command programs four previously erased bytes in the program flash memory using an embedded algorithm CAUTION A flash memory loca...

Page 917: ...andling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR An invalid flash address is supplied FSTAT ACCERR Flash address is not longword aligned FSTAT ACCERR Flash...

Page 918: ...e flash sector to be erased 3 Flash address 7 0 1 in the flash sector to be erased 1 Must be longword aligned flash address 1 0 00 After clearing CCIF to launch the Erase Flash Sector command the flas...

Page 919: ...ash Sector Operation If the ERSSUSP bit is still set when CCIF is cleared to launch the next command the previous Erase Flash Sector operation resumes The flash memory module acknowledges the request...

Page 920: ...ased state Data in this sector is not reliable until a new erase command fully completes The following figure shows how to suspend and resume the Erase Flash Sector operation Functional Description KL...

Page 921: ...xecute Yes DONE No ERSSUSP 1 Save Erase Algo Set CCIF No Yes Start New Resume Erase No Abort User Cmd Interrupt Suspend Set SUSPACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Complete...

Page 922: ...the FSEC SEC field to the unsecure state The security byte in the flash configuration field see Flash Configuration Field Description remains unaffected by the Read 1s All Blocks command If the read f...

Page 923: ...for the Read Once command range from 0x00 0x0F During execution of the Read Once command any attempt to read addresses within the program flash block containing the selected record index returns inval...

Page 924: ...0x0F During execution of the Program Once command any attempt to read addresses within the program flash block containing the selected record index returns invalid data Table 45 28 Program Once Comma...

Page 925: ...fashion outside of the flash memory Refer to the device s Chip Configuration details for information on this functionality Before invoking the external erase all function the FSTAT ACCERR and PVIOL fl...

Page 926: ...son key in the Flash Configuration Field If the backdoor keys match the FSEC SEC field is changed to the unsecure state and security is released If the backdoor keys do not match security is not relea...

Page 927: ...nsecure operation completes Table 45 34 Erase All Blocks Unsecure Command Error Handling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR Any errors have been enco...

Page 928: ...rogram flash erase and program commands are available and that the region of the program flash containing the flash configuration field is unprotected If the flash security byte is successfully progra...

Page 929: ...omparison fails After the backdoor keys have been correctly matched the chip is unsecured by changing the FSEC SEC bits A successful execution of the Verify Backdoor Access Key command changes the sec...

Page 930: ...rked by setting CCIF which enables flash user commands If a reset occurs while any flash command is in progress that command is immediately aborted The state of the word being programmed or the sector...

Page 931: ...Kinetis ROM Bootloader chapter Added ReadMemory command in Table 13 2 Commands supported by the Kinetis Bootloader in ROM Updated descriptions of the following configuration fields enabledPeripherals...

Page 932: ...changes No substantial content changes A 9 Security chapter changes No substantial content changes A 10 Debug chapter changes No substantial content changes A 11 Pinouts chapter changes Added signal...

Page 933: ...he Description Field of Configuration Fields for the Kinetis Bootloader table Updated FlashEraseAll command section In topic Start up Process updated labels in the figure Kinetis Bootloader Start up F...

Page 934: ...LWU changes No substantial content changes A 20 AIPS module changes Changed the reset value of Master Privilege Register A AIPS_MPRA to 0000_0000h Edited General operation A 21 DMAMUX module changes R...

Page 935: ...nal Voltage Regulator topic to the chapter A 28 MCG_Lite changes No substantial changes A 29 OSC changes No substantial content changes A 30 TPM changes Updated MOD MOD and CnV VAL fields descriptions...

Page 936: ...nsceiver required external components In the first bullet removed reference to the bitfield USB_OTGCTL DPHIGH Replaced figure Typical Device only block diagram bus powered with new figure Typical Devi...

Page 937: ...o substantial content changes A 40 FlexIO changes No substantial content changes A 41 I2S SAI changes Removed a note about data lines and channels which does not apply to this device A 42 GPIO changes...

Page 938: ...o substantial content changes A 45 FMC changes No substantial content changes A 46 FTFA changes No substantial content changes MTB configuration changes KL27 Sub Family Reference Manual Rev 5 01 2016...

Page 939: ...al parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including...

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