SAMPLES
Rx pin input
RT CLOCK
RT CLOCK COUNT
RESET RT CLOCK
1
1
1
1
0
START BIT
LSB
R
T1
R
T1
R
T1
R
T1
R
T1
R
T1
R
T1
R
T1
R
T1
R
T2
R
T3
R
T4
R
T5
R
T6
R
T2
R
T3
R
T4
R
T7
R
T8
R
T9
R
T1
1
R
T1
3
R
T1
4
R
T1
5
R
T1
6
1
1
1
1
0
0
0
0
0
0
R
T1
0
R
T1
2
R
T1
START BIT
QUALIFICATION
DATA
SAMPLING
START BIT
VERIFICATION
Figure 38-3. Receiver data sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5,
and RT7 when C7816[ISO_7816E] is cleared/disabled and RT8, RT9 and RT10 when
C7816[ISO_7816E] is set/enabled. The following table summarizes the results of the start
bit verification samples.
Table 38-4. Start bit verification
RT3, RT5, and RT7 samples
RT8, RT9, RT10 samples when 7816E
Start bit verification
Noise flag
000
Yes
0
001
Yes
1
010
Yes
1
011
No
0
100
Yes
1
101
No
0
110
No
0
111
No
0
If start bit verification is not successful, the RT clock is reset and a new search for a start
bit begins.
To determine the value of a data bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10. The following table summarizes the results of the data bit samples.
Table 38-5. Data bit recovery
RT8, RT9, and RT10 samples
Data bit determination
Noise flag
000
0
0
001
0
1
010
0
1
011
1
1
Table continues on the next page...
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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