NXP Semiconductors MKL27Z128VFM4, Reference Manual

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Table 10-6. ADC0 signal descriptions (continued)
Chip signal name Module signal
name
Description I/O
VDDA V
DDA
Analog Power Supply I
VSSA V
SSA
Analog Ground I
EXTRG_IN ADHWT Hardware trigger I
This table presents the signal descriptions of the CMP0 module.
Table 10-7. CMP0 signal descriptions
Chip signal name Module signal
name
Description I/O
CMP0_IN[5:0] IN[5:0] Analog voltage inputs I
CMP0_OUT CMPO Comparator output O
This table presents the signal descriptions of the DAC0 module.
Table 10-8. DAC0 signal descriptions
Chip signal name Module signal
name
Description I/O
DAC0_OUT — DAC output O
Table 10-9. VREF signal descriptions
Chip signal name Module signal
name
Description I/O
VREF_OUT VREF_OUT Internally-generated voltage reference output O
10.5.5 Timer Modules
Table 10-10. TPM0 signal descriptions
Chip signal name Module signal
name
Description I/O
TPM_CLKIN[1:0] TPM_EXTCLK External clock. TPM external clock can be selected to increment the
TPM counter on every rising edge synchronized to the counter
clock. I
TPM0_CH[5:0] TPM_CHn TPM channel (n = 5 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input. I/O
Module Signal Description Tables
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
120 Freescale Semiconductor, Inc.