29.5.9 DMA
The channel and overflow flags generate a DMA transfer request according to DMA and
CHnIE/TOIE bits.
See the following table for more information.
Table 29-6. DMA Transfer Request
DMA
CHnIE/
TOIE
Channel/Overflow DMA Transfer Request
Channel/Overflow Interrupt
0
0
The channel/overflow DMA transfer request is
not generated.
The channel/overflow interrupt is not generated.
0
1
The channel/overflow DMA transfer request is
not generated.
The channel/overflow interrupt is generated if
(CHnF/TOF = 1).
1
0
The channel/overflow DMA transfer request is
generated if (CHnF/TOF = 1).
The channel/overflow interrupt is not generated.
1
1
The channel/overflow DMA transfer request is
generated if (CHnF/TOF = 1).
The channel/overflow interrupt is generated if
(CHnF/TOF = 1).
If DMA = 1, the CHnF/TOF bit can be cleared either by DMA transfer done or writing a
one to CHnF/TOF bit (see the following table).
Table 29-7. Clear CHnF/TOF Bit
DMA
How CHnF/TOF Bit Can Be Cleared
0
CHnF/TOF bit is cleared by writing a 1 to CHnF/TOF bit.
1
CHnF/TOF bit is cleared either when the DMA transfer is done or by writing a 1 to CHnF/TOF bit.
29.5.10 Output triggers
The TPM generates output triggers for the counter and each channel that can be used to
trigger events in other peripherals.
The counter trigger asserts whenever the TOF is set and remains asserted until the next
increment.
Each TPM channel generates both a pre-trigger output and a trigger output. The pre-
trigger output asserts whenever the CHnF is set, the trigger output asserts on the first
counter increment after the pre-trigger asserts, and then both the trigger and pre-trigger
negate on the first counter increment after the trigger asserts.
Chapter 29 Timer/PWM Module (TPM)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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