18.3 LLWU signal descriptions
The signal properties of LLWU are shown in the table found here.
The external wakeup input pins can be enabled to detect either rising-edge, falling-edge,
or on any change.
Table 18-2. LLWU signal descriptions
Signal
Description
I/O
LLWU_Pn
Wakeup inputs (n = 0-15 )
I
18.4 Memory map/register definition
The LLWU includes the following registers:
• Wake-up source enable registers
• Enable external pin input sources
• Enable internal peripheral interrupt sources
• Wake-up flag registers
• Indication of wakeup source that caused exit from a low-leakage power mode
includes external pin or internal module interrupt
• Wake-up pin filter enable registers
NOTE
The LLWU registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
All LLWU registers are reset by Chip Reset not VLLS and by
reset types that trigger Chip Reset not VLLS. Each register's
displayed reset value represents this subset of reset types.
LLWU registers are unaffected by reset types that do not trigger
Chip Reset not VLLS. For more information about the types of
reset on this chip, refer to the
Chapter 18 Low-Leakage Wakeup Unit (LLWU)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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