5.7.10 I
2
S/SAI clocking
The audio master clock (MCLK) is used to generate the bit clock when the receiver or
transmitter is configured for an internally generated bit clock. The audio master clock can
also be output to or input from a pin. The transmitter and receiver have the same audio
master clock inputs.
Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock.
The I
2
S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can
be generated internally from the audio master clock or supplied externally. The module
also supports the option for synchronous operation between the receiver and transmitter.
The transmitter and receiver can independently select between the bus clock and the
audio master clock to generate the bit clock.
The MCLK and BCLK source options appear in the following figure.
1
0
11
01
10
00
OSCERCLK
MCGPCLK
System Clock
I2Sx_MCR[MOE]
MCLK
MCLK_OUT
MCLK_IN
11
01
10
00
Bus Clock
[MSEL]
Bit
Clock
Divider
1
0
BCLK_IN
I2S/SAI
BCLK_OUT
[BCD]
BCLK
I2Sx_MCR[MICS]
Clock Generation
[DIV]
I2Sx_TCR2/RCR2
Direction
Control
Pad Interface Logic
MCGIRCLK
Figure 5-10. I
2
S/SAI clock generation
Module clocks
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
78
Freescale Semiconductor, Inc.
