35.5.5.1 Transmit by DMA
Transmit by DMA is supported only when TXDMAE is set. A transmit DMA request is
asserted when both SPE and SPTEF are set. Then the on-chip DMA controller detects
this request and transfers data from memory into the SPI data register. After that, TX
DMA DONE is asserted to clear SPTEF automatically. This process repeats until all data
for transmission (the number is decided by the configuration register[s] of the DMA
controller) is sent.
When the FIFO feature is supported: In FIFO mode (FIFOMODE=1) and when a data
length of 8 bits is selected (SPIMODE=0), the DMA transfer for one transmit DMA
request can write more than 1 byte (up to 8 bytes) to the DL register because the TX
FIFO can store 8 bytes of transmit data. In FIFO mode (FIFOMODE=1) and when a data
length of 16 bits is selected (SPIMODE=1), the DMA transfer for one transmit DMA
request can write more than 1 word (up to 4 words) to the DH:DL registers because the
TX FIFO can store 4 words of transmit data. A larger number of bytes or words
transferred from memory to the SPI data register for each transmit DMA request results
in a lower total number of transmit DMA requests.
When FIFOMODE is 0: Cycle Steal (DMA_DCRn[CS] = 1) should be enabled when
using the DMA controller to transfer data from memory to the SPI data register. The
DMA performs a single data transfer per DMA request in cycle steal mode. Therefore, a
single byte/word is written to the SPI data register from memory and transmitted by the
SPI module for each DMA request, as long as the BCR value is greater than zero
(DMA_DSR_BCRn[BCR] > 0). Once the BCR has reached zero, software must
reconfigure the DMA controller if more data is to be transmitted. If a configuration error
occurs (DMA_DSR_BCRn[CE] = 1) when the BCR is equal to 0, software must:
• disable peripheral requests when the BCR is equal to 0,
• perform 16-bit transfers (SPIMODE = 1), or
• decrease the SPI baud rate.
Software can disable peripheral requests by setting DMA_DCRn[D_REQ] = 1 when
initializing the DMA controller, or by clearing DMA_DCRn[ERQ] once the BCR is
equal to zero. Also, to continue transmitting data software must re-enable peripheral
requests (DMA_DCRn[ERQ] = 1) after reconfiguring the DMA controller.
35.5.5.2 Receive by DMA
Receive by DMA is supported only when RXDMAE is set. A receive DMA request is
asserted when both SPE and SPRF are set. Then the on-chip DMA controller detects this
request and transfers data from the SPI data register into memory. After that, RX DMA
DONE is asserted to clear SPRF automatically. This process repeats until all data to be
Chapter 35 Serial Peripheral Interface (SPI)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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