38.5.2.6 Receiving break characters
The UART recognizes a break character when a start bit is followed by eight, nine, or ten
logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character
has these effects on UART registers:
• Sets the framing error flag, S1[FE].
• Writes an all 0 dataword to the data buffer, which may cause S1[RDRF] to set,
depending on the watermark and number of values in the data buffer.
• May set the overrun flag, S1[OR], noise flag, S1[NF], parity error flag, S1[PE], or
the receiver active flag, S2[RAF].
The UART break character detection threshold depends on C1[M], C1[PE] and C4[M10].
See the following table.
Table 38-7. Receive break character detection threshold
M
M10
PE
Threshold (bits)
0
—
—
10
1
0
—
11
1
1
1
12
Break characters are not detected or supported when C7816[ISO_7816E] is set/enabled.
38.5.2.7 Baud rate tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud
rate. Accumulated bit time misalignment can cause one of the three stop bit data samples
(RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the
RT8, RT9, and RT10 samples are not all the same logical values. A framing error will
occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9,
and RT10 stop bit samples are a logic 0.
As the receiver samples an incoming frame, it resynchronizes the RT clock on any valid
falling edge within the frame. Resynchronization within frames corrects a misalignment
between transmitter bit times and receiver bit times.
38.5.2.7.1 Slow data tolerance
The following figure shows how much a slow received frame can be misaligned without
causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1
but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
Functional description
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
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Freescale Semiconductor, Inc.
