25.5.1.1 DAC data buffer interrupts
There are several interrupts and associated flags that can be configured for the DAC
buffer. SR[DACBFRPBF] is set when the DAC buffer read pointer reaches the DAC
buffer upper limit, that is, C2[DACBFRP] = C2[DACBFUP]. SR[DACBFRPTF] is set
when the DAC read pointer is equal to the start position, 0.
25.5.1.2 Modes of DAC data buffer operation
The following table describes the different modes of data buffer operation for the DAC
module.
Table 25-1. Modes of DAC data buffer operation
Modes
Description
Buffer Normal mode
This is the default mode. The buffer works as a circular buffer.
The read pointer increases by one, every time the trigger
occurs. When the read pointer reaches the upper limit, it goes
to 0 directly in the next trigger event.
Buffer One-time Scan mode
The read pointer increases by 1 every time the trigger occurs.
When it reaches the upper limit, it stops there. If read pointer
is reset to the address other than the upper limit, it will
increase to the upper address and stop there again.
NOTE: If the software set the read pointer to the upper limit,
the read pointer will not advance in this mode.
FIFO Mode
In FIFO mode, the buffer is organized as a FIFO. For a valid
write to any DACDATx, the data is put into the FIFO, and the
write pointer is automatically incremented. The module is
connected internally to a 32bit interface. For any 16bit or 8bit
FIFO access, address bit[1] needs to be 0; otherwise, the
write is ignored. For any 32bit FIFO access, the Write_Pointer
needs to be an EVEN number; otherwise, the write is ignored.
NOTE: A successful 32bit FIFO write will increase the write
pointer by 2. Any write will cause the FIFO over-flow
will be ignored, the cases includes: 1.FIFO is full, the
write will be ignored. 2.FIFO is nearly full
(FIFO_SIZE-1), 32bit write will be ignored.
NOTE: For 8bit write, address bit[0] determine which byte
lane will be written to the FIFO according to little
endian alignment. Only both byte lanes are written
will the write pointer increase. User need to make
sure 8bit access happened in pair and both upper &
lower bytes are written. There is no requirement on
which byte write first. In FIFO mode, there is no
change to read access of DACDATx (from normal
mode), read to DACDATx will return the DATA
addressed by the access address to the data buffer,
and both write pointer and read pointer in FIFO mode
will NOT be changed by read access. FIFO write can
Functional description
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
420
Freescale Semiconductor, Inc.
