Clock
Max. Frequency
MCGIRCLK
8 MHz
MCGPCLK
48 MHz
5.5.1 Clock divider values after reset
Each clock divider is programmed via the CLKDIV1 registers of the SIM module. Two
bits in the flash memory's FTFA_FOPT register control the reset value of the core clock,
system clock, bus clock, and flash clock dividers as shown in the table given below:
FTFA_FOPT [4,0]
Core/system clock
Bus/Flash clock
Execution Mode
00
0x7 (divide by 8)
0x1 (divide by 2)
VLPR
01
0x3 (divide by 4)
0x1 (divide by 2)
VLPR
10
0x1 (divide by 2)
0x1 (divide by 2)
RUN
11
0x0 (divide by 1)
0x1 (divide by 2)
RUN
This gives the user flexibility in selecting between a lower frequency, low-power boot
option and higher frequency, higher power during and after reset.
The flash erased state defaults to fast clocking mode, since these bits reside in flash,
which is logic 1 in the flash erased state. To enable a lower power boot option, program
the appropriate bits in FTFA_FOPT. During the reset sequence, if either of the control
bits is cleared, the system is in a slower clock configuration. Upon any system reset, the
clock dividers return to this configurable reset state.
The default reset clock for core/system clock is 8 MHz from IRC8M.
5.5.2 VLPR mode clocking
The clock dividers cannot be changed while in VLPR mode. These dividers must be
programmed prior to entering VLPR mode to guarantee operation. Maximum frequency
limitations for VLPR mode is as follows :
• the core/system clocks are less than or equal to 4 MHz, and
• the bus and flash clocks are less than or equal to 1 MHz
Internal clocking requirements
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
70
Freescale Semiconductor, Inc.
