NXP Semiconductors MKL27Z128VFM4, Reference Manual

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LPUARTx_STAT field descriptions (continued)
Field Description
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
37.3.3 LPUART Control Register (LPUARTx_CTRL)
This read/write register controls various optional features of the LPUART system. This
register should only be altered when the transmitter and receiver are both disabled.
Address: Base a 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
R8T9 R9T8
TXDIR TXINV
ORIE NEIE FEIE PEIE TIE TCIE RIE ILIE TE RE RWU SBK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MA1IE MA2IE
0
IDLECFG
LOOPS
DOZEEN
RSR
C
M
WAKE
ILT PE PT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPUARTx_CTRL field descriptions
Field Description
31
R8T9
Receive Bit 8 / Transmit Bit 9
R8 is the ninth data bit received when the LPUART is configured for 9-bit or 10-bit data formats. When
reading 9-bit or 10-bit data, read R8 before reading LPUART_DATA.
T9 is the tenth data bit received when the LPUART is configured for 10-bit data formats. When writing 10-
bit data, write T9 before writing LPUART_DATA. If T9 does not need to change from its previous value,
such as when it is used to generate address mark or parity, they it need not be written each time
LPUART_DATA is written.
30
R9T8
Receive Bit 9 / Transmit Bit 8
R9 is the tenth data bit received when the LPUART is configured for 10-bit data formats. When reading
10-bit data, read R9 before reading LPUART_DATA
T8 is the ninth data bit received when the LPUART is configured for 9-bit or 10-bit data formats. When
writing 9-bit or 10-bit data, write T8 before writing LPUART_DATA. If T8 does not need to change from its
previous value, such as when it is used to generate address mark or parity, they it need not be written
each time LPUART_DATA is written.
Table continues on the next page...
Register definition
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
658 Freescale Semiconductor, Inc.