NXP Semiconductors MKL27Z128VFM4, Reference Manual

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Table 10-21. LPUART0 signal descriptions
Chip signal name Module signal
name
Description I/O
LPUART0_TX TxD Transmit data O
LPUART0_RX RxD Receive data I
Table 10-22. LPUART1 signal descriptions
Chip signal name Module signal
name
Description I/O
LPUART1_TX TxD Transmit data I/O
LPUART1_RX RxD Receive data I
Table 10-23. UART2 signal descriptions
Chip signal name Module signal
name
Description I/O
UART2_TX TxD Transmit data O
UART2_RX RxD Receive data I
Table 10-24. I
2
S0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
I2S0_MCLK SAI_MCLK Audio Master Clock. The master clock is an input when externally
generated and an output when internally generated. I/O
I2S0_RX_BCLK SAI_RX_BCLK Receive Bit Clock. The bit clock is an input when externally
generated and an output when internally generated. I/O
I2S0_RX_FS SAI_RX_SYNC Receive Frame Sync. The frame sync is an input sampled
synchronously by the bit clock when externally generated and an
output generated synchronously by the bit clock when internally
generated. I/O
I2S0_RXD SAI_RX_DATA[1:0] Receive Data. The receive data is sampled synchronously by the
bit clock.
I
I2S0_TX_BCLK SAI_TX_BCLK Transmit Bit Clock. The bit clock is an input when externally
generated and an output when internally generated. I/O
I2S0_TX_FS SAI_TX_SYNC Transmit Frame Sync. The frame sync is an input sampled
synchronously by the bit clock when externally generated and an
output generated synchronously by the bit clock when internally
generated. I/O
I2S0_TXD SAI_TX_DATA[1:0] Transmit Data. The transmit data is generated synchronously by
the bit clock and is tristated whenever not transmitting a word.
O
Chapter 10 Pinouts and Packaging
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc. 123