Between these two successive transmissions, no pause is inserted; the SS pin remains
low.
The following figure shows the clock formats when SPIMODE = 0 and C1[CPHA] = 0.
At the top of the figure, the eight bit times are shown for reference with bit 1 starting as
the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB
first and LSB first lines show the order of SPI data bits depending on the setting in
LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms
applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN
waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI
waveform applies to the MOSI output pin from a master and the MISO waveform applies
to the MISO output from a slave. The SS OUT waveform applies to the slave select
output from a master (provided C2[MODFEN] and C1[SSOE] = 1). The master SS
output goes to active low at the start of the first bit time of the transfer and goes back
high one-half SPSCK cycle after the end of the eighth bit time of the transfer. The SS IN
waveform applies to the slave select input of a slave.
SS OUT
SS IN
(SLAVE)
(MASTER)
(SLAVE OUT)
MISO
MSB FIRST
LSB FIRST
MOSI
(MASTER OUT)
(MISO OR MOSI)
SAMPLE IN
SPSCK
(CPOL = 1)
SPSCK
(CPOL = 0)
BIT TIME #
(REFERENCE)
BIT 7
BIT 0
BIT 6
BIT 1
BIT 2
BIT 5
BIT 0
BIT 7
BIT 1
BIT 6
1
2
6
7
8
...
...
...
Figure 35-8. SPI clock formats (CPHA = 0)
Chapter 35 Serial Peripheral Interface (SPI)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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