NOTE
When the FIFO is not supported or not enabled (FIFOMODE is
not present or is 0): Bits 3 through 0 are not implemented and
always read 0.
When the FIFO is supported and enabled (FIFOMODE is 1): This register has four flags
that provide mechanisms to support an 8-byte FIFO mode: RNFULLF, TNEARF,
TXFULLF, and RFIFOEF. When the SPI is in 8-byte FIFO mode, the function of SPRF
and SPTEF differs slightly from their function in the normal buffered modes, mainly
regarding how these flags are cleared by the amount available in the transmit and receive
FIFOs.
• The RNFULLF and TNEAREF help improve the efficiency of FIFO operation when
transfering large amounts of data. These flags provide a "watermark" feature of the
FIFOs to allow continuous transmissions of data when running at high speed.
• The RNFULLF can generate an interrupt if the RNFULLIEN bit in the C3 register is
set, which allows the CPU to start emptying the receive FIFO without delaying the
reception of subsequent bytes. The user can also determine if all data in the receive
FIFO has been read by monitoring the RFIFOEF.
• The TNEAREF can generate an interrupt if the TNEARIEN bit in the C3 register is
set, which allows the CPU to start filling the transmit FIFO before it is empty and
thus to prevent breaks in SPI transmission.
NOTE
At an initial POR, the values of TNEAREF and RFIFOEF are
0. However, the status (S) register and both TX and RX FIFOs
are reset due to a change of SPIMODE, FIFOMODE or SPE. If
this type of reset occurs and FIFOMODE is 0, TNEAREF and
RFIFOEF continue to reset to 0. If this type of reset occurs and
FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
Address: Base a 0h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
1
0
0
0
0
0
SPIx_S field descriptions
Field
Description
7
SPRF
SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when
FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): SPRF is set at the
completion of an SPI transfer to indicate that received data may be read from the SPI data (DH:DL)
register. When the receive DMA request is disabled (RXDMAE is 0), SPRF is cleared by reading SPRF
while it is set and then reading the SPI data register. When the receive DMA request is enabled (RXDMAE
Table continues on the next page...
Chapter 35 Serial Peripheral Interface (SPI)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
575
