19.2.2 General operation
The slave devices connected to the peripheral bridge are modules which contain a
programming model of control and status registers. The system masters read and write
these registers through the peripheral bridge.
The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is
allocated one or more 4-KB block(s) of the memory map.
19.3 Memory map/register definition
AIPS memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
0
Master Privilege Register A (AIPS_MPRA)
32
R/W
20
Peripheral Access Control Register (AIPS_PACRA)
32
R/W
24
Peripheral Access Control Register (AIPS_PACRB)
32
R/W
28
Peripheral Access Control Register (AIPS_PACRC)
32
R/W
2C
Peripheral Access Control Register (AIPS_PACRD)
32
R/W
40
Peripheral Access Control Register (AIPS_)
32
R/W
19.3.1 Master Privilege Register A (AIPS_MPRA)
The MPRA specifies identical 4-bit fields defining the access-privilege level associated
with a bus master to various peripherals on the chip. The register provides one field per
bus master.
NOTE
At reset, the default value loaded into the MPRA fields is chip-
specific. See the chip configuration details for the value of a
particular device.
A register field that maps to an unimplemented master or peripheral behaves as read-
only-zero.
Each master is assigned a logical ID from 0 to 15. See the master logical ID assignment
table in the chip-specific AIPS information.
Memory map/register definition
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
284
Freescale Semiconductor, Inc.
