![NXP Semiconductors MKL27Z128VFM4 Reference Manual Download Page 476](http://html1.mh-extra.com/html/nxp-semiconductors/mkl27z128vfm4/mkl27z128vfm4_reference-manual_1721847476.webp)
The TPM period when using up counting is (MOD + 0x0001) × period of the TPM
counter clock.
The TOF bit is set when the TPM counter changes from MOD to zero.
MOD = 0x0004
TOF bit
3
4
0
0
1
1
2
2
3
3
4
4
0
1
2
timer module counter
set TOF bit
period of timer module counter clock
period of counting = (MOD + 0x0001) x period of timer module counter clock
set TOF bit
set TOF bit
Figure 29-3. Example of TPM Up Counting
Note
• MOD = 0000 is a redundant condition. In this case, the
TPM counter is always equal to MOD and the TOF bit is
set in each rising edge of the TPM counter clock.
29.5.3.2 Up-down counting
Up-down counting is selected when SC[CPWMS] = 1. When configured for up-down
counting, configuring CONF[MOD] to less than 2 is not supported.
The value of 0 is loaded into the TPM counter, and the counter increments until the value
of MOD is reached, at which point the counter is decremented until it returns to zero and
the up-down counting restarts.
The TPM period when using up-down counting is 2 × MOD × period of the TPM counter
clock.
The TOF bit is set when the TPM counter changes from MOD to (MOD – 1).
Functional description
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
476
Freescale Semiconductor, Inc.