NXP Semiconductors MKL27Z128VFM4, Reference Manual

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Table 2-11. Module-to-module interconnects (continued)
Peripheral Signal — to
Peripheral
Use Case Control Comment
PIT TIF0 to DMA CH0 DMA HW
Trigger
DMA MUX register option —
PIT TIF1 to DMA CH1 DMA HW
Trigger
DMA MUX register option —
Table 2-12. Module-to-FlexIO interconnects
Peripheral Signal — to
Peripheral
Use Case Control Comment
LPTMR Hardware
trigger
to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
—
TPMx TOF to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
—
PIT CHx TIF0, TIF1 to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
If PIT is triggering
the FlexIO, the
FlexIO clock must be
faster than Bus
clock.
RTC ALARM or
SECONDS
to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
—
EXTRG_IN EXTRG_IN to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
—
CMP0 CMP0_OUT to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit
field)
—
2.3.2 Analog reference options
Several analog blocks have selectable reference voltages as shown in the below table .
These options allow analog peripherals to share or have separate analog references. Care
should be taken when selecting analog references to avoid cross talk noise.
Table 2-13. Analog reference options
Module Reference option Comment/ Reference selection
16-bit SAR ADC 1 - VREFH or 1.2V VREF_OUT
2 - VDDA
3 - Reserved
Selected by ADCx_SC2[REFSEL]
12-bit DAC 1 - VREFH or 1.2V VREF_OUT
2 - VDDA
1
Selected by DACx_C0[DACRFS] bit
CMP with 6-bit DAC Vin1 - VREFH or 1.2V VREF_OUT
Vin2 - VDD
1
Selected by CMPx_DACCR[VRSEL]
Chapter 2 Introduction
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc. 47