29.4.1 Status and Control (TPMx_SC)
SC contains the overflow status flag and control bits used to configure the interrupt
enable, module configuration and prescaler factor. These controls relate to all channels
within this module.
Address: Base a 0h offset
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TPMx_SC field descriptions
Field
Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
DMA
DMA Enable
Enables DMA transfers for the overflow flag.
0
Disables DMA transfers.
1
Enables DMA transfers.
7
TOF
Timer Overflow Flag
Set by hardware when the TPM counter equals the value in the MOD register and increments. Writing a 1
to TOF clears it. Writing a 0 to TOF has no effect.
If another TPM overflow occurs between the flag setting and the flag clearing, the write operation has no
effect; therefore, TOF remains set indicating another overflow has occurred. In this case a TOF interrupt
request is not lost due to a delay in clearing the previous TOF.
Table continues on the next page...
Chapter 29 Timer/PWM Module (TPM)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
463
