NXP Semiconductors MKL27Z128VFM4, Reference Manual

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Table 5-2. Module clocks (continued)
Module Bus interface clock Internal clocks I/O interface clocks
ADC Bus clock OSCERCLK —
CMP Bus clock — —
DAC Bus clock — —
Internal Voltage Reference
(VREF)
Bus clock — —
Timers
TPM Bus clock TPM clock TPM_CLKIN0, TPM_CLKIN1
PIT Bus clock — —
LPTMR Bus clock LPO, OSCERCLK,
MCGPCLK, ERCLK32K
—
RTC Bus clock ERCLK32K RTC_CLKOUT, RTC_CLKIN
Communication interfaces
USB FS (Device Only) System clock USB FS clock —
SPI0 Bus clock — SPI0_SCK
SPI1 System clock — SPI1_SCK
I
2
C0 System Clock — I2C0_SCL
I
2
C1 System Clock — I2C1_SCL
LPUART0, LPUART1 Bus clock LPUART0 clock
LPUART1 clock
—
UART2 Bus clock — —
FlexIO Bus clock FlexIO clock —
I
2
S Bus clock I
2
S master clock I2S_TX_BCLK,
I2S_RX_BCLK
Human-machine interfaces
GPIO Platform clock — —
5.7.1 PMC 1-kHz LPO clock
The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all
modes of operation, including all low-power modes except VLLS0. This 1-kHz source is
commonly referred to as LPO clock or 1-kHz LPO clock.
5.7.2 COP clocking
The COP may be clocked from four clock sources as shown in the following figure.
Module clocks
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
72 Freescale Semiconductor, Inc.