39.3.16 Shifter Buffer N Bit Byte Swapped Register
(FLEXIO_SHIFTBUFBBSn)
.
Address: 4005_F000h base + 380h (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLEXIO_SHIFTBUFBBSn field descriptions
Field
Description
SHIFTBUFBBS Shift Buffer
Alias to SHIFTBUF register, except reads/writes to this register are bit swapped within each byte. Reads
return { SHIFTBUF[24:31], SHIFTBUF[16:23], SHIFTBUF[8:15], SHIFTBUF[0:7] }.
39.3.17 Timer Control N Register (FLEXIO_TIMCTLn)
.
Address: 4005_F000h base + 400h (4d × i), where i=0d to 3d
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLEXIO_TIMCTLn field descriptions
Field
Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
TRGSEL
Trigger Select
The valid values for TRGSEL will depend on the FLEXIO_PARAM register.
Table continues on the next page...
Memory Map and Registers
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
762
Freescale Semiconductor, Inc.
