in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was
in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output
from the master and an input to the slave. The slave device must be selected by a low
level on the slave select input (SS pin). In this system, the master device has configured
its SS pin as an optional slave select output.
SPI SHIFTER
MASTER
8 OR 16 BITS
CLOCK
GENERATOR
MOSI
MISO
MISO
MOSI
SPSCK
SPSCK
SS
SS
SLAVE
SPI SHIFTER
8 OR 16 BITS
Figure 35-1. SPI system connections
35.2.3.2 SPI module block diagram
The following is a block diagram of the SPI module. The central element of the SPI is the
SPI shift register. Data is written to the double-buffered transmitter (write to
SPIx_DH:SPIx_DL) and gets transferred to the SPI Shift Register at the start of a data
transfer. After shifting in 8 bits or 16 bits (as determined by the SPIMODE bit) of data,
the data is transferred into the double-buffered receiver where it can be read from
SPIx_DH:SPIx_DL. Pin multiplexing logic controls connections between MCU pins and
the SPI module.
When the FIFO feature is supported: Additionally there is an 8-byte receive FIFO and an
8-byte transmit FIFO that (once enabled) provide features to allow fewer CPU interrupts
to occur when transmitting/receiving high volume/high speed data. When FIFO mode is
enabled, the SPI can still function in either 8-bit or 16-bit mode (as per SPIMODE bit)
and three additional flags help monitor the FIFO status. Two of these flags can provide
CPU interrupts.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the
shifter output is routed to MOSI, and the shifter input is routed from the MISO pin.
Introduction
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
570
Freescale Semiconductor, Inc.
