• Additional access semantics encoded into the reference address
• Resides between a crossbar switch slave port and a peripheral bridge bus controller
• Two-stage pipeline design matching the AHB system bus protocol
• Combinationally passes non-decorated accesses to peripheral bridge bus controller
• Conversion of decorated loads and stores from processor core into atomic read-
modify-writes
• Decorated loads support unsigned bit field extracts, load-and-{set,clear} 1-bit
operations
• Decorated stores support bit field inserts, logical AND, OR, and XOR operations
• Support for byte, halfword and word-sized decorated operations
• Supports minimum signal toggling on AHB output bus to reduce power dissipation
42.1.3 Modes of operation
The BME module does not support any special modes of operation. As a memory-
mapped device located on a crossbar slave AHB system bus port, BME responds strictly
on the basis of memory addresses for accesses to the peripheral bridge bus controller.
All functionality associated with the BME module resides in the core platform's clock
domain; this includes its connections with the crossbar slave port and the PBRIDGE bus
controller.
42.2 Memory map and register definition
The BME module provides a memory-mapped capability and does not include any
programming model registers.
The exact set of functions supported by the BME are detailed in the
.
The peripheral address space occupies a 516 KB region: 512 KB based at 0x4000_0000
plus a 4 KB space based at 0x400F_F000 for GPIO accesses; the decorated address space
is mapped to the 448 MB region located at 0x4400_0000–0x5FFF_FFFF.
42.3 Functional description
Information found here details the specific functions supported by the BME.
Chapter 42 Bit Manipulation Engine (BME)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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