23.5.4.3 Aborting conversions
Any conversion in progress is aborted when:
• Writing to SC1A while it is actively controlling a conversion, aborts the current
conversion. In Software Trigger mode, when SC2[ADTRG]=0, a write to SC1A
initiates a new conversion if SC1A[ADCH] is equal to a value other than all 1s.
Writing to any of the SC1B–SC1n registers while that specific SC1B–SC1n register
is actively controlling a conversion aborts the current conversion. The SC1(B-n)
registers are not used for software trigger operation and therefore writes to the
SC1(B-n) registers do not initiate a new conversion.
• A write to any ADC register besides the SC1A-SC1n registers occurs. This indicates
that a change in mode of operation has occurred and the current conversion is
therefore invalid.
• The MCU is reset or enters Low-Power Stop modes.
• The MCU enters Normal Stop mode with ADACK or Alternate Clock Sources not
enabled.
When a conversion is aborted, the contents of the data registers, Rn, are not altered. The
data registers continue to be the values transferred after the completion of the last
successful conversion. If the conversion was aborted by a reset or Low-Power Stop
modes, RA and Rn return to their reset states.
23.5.4.4 Power control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is
selected as the conversion clock source, but the asynchronous clock output is disabled,
that is CFG2[ADACKEN]=0, the ADACK clock generator also remains in its idle state
(disabled) until a conversion is initiated. If the asynchronous clock output is enabled, that
is, CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the
MCU power mode.
Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC].
This results in a lower maximum value for f
ADCK
.
Functional description
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
368
Freescale Semiconductor, Inc.
