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5.6 Clock gating
The clock to each module can be individually gated on and off using bits of the SCGCx
registers of the SIM module. These bits are cleared after any reset, which disables the
clock to the corresponding module to conserve power. Prior to initializing a module, set
the corresponding bit in the SCGCx register to enable the clock. Before turning off the
clock, make sure to disable the module.
Any bus access to a peripheral that has its clock disabled generates an error termination.
5.7 Module clocks
The following table summarizes the clocks associated with each module.
Table 5-2. Module clocks
Module
Bus interface clock
Internal clocks
I/O interface clocks
Core modules
ARM Cortex-M0+ core
Platform clock
Core clock
—
NVIC
Platform clock
—
—
DAP
Platform clock
—
SWD_CLK
System modules
DMA
System clock
—
—
DMA Mux
Bus clock
—
—
Port control
Bus clock
—
—
Crossbar Switch
Platform clock
—
—
Peripheral bridges
System clock
Bus clock
—
LLWU, PMC, SIM, RCM
Bus clock
LPO
—
Mode controller
Bus clock
—
—
MCM
Platform clock
—
—
COP watchdog
Bus clock
LPO, Bus Clock, MCGIRCLK,
OSCERCLK
—
Clocks
MCG_Lite
Bus clock
MCGOUTCLK, MCGPCLK,
MCGIRCLK, OSCERCLK,
ERCLK32K
—
OSC
Bus clock
OSCERCLK
—
Memory and memory interfaces
Flash Controller
Platform clock
Flash clock
—
Flash memory
Flash clock
—
—
Analog
Table continues on the next page...
Chapter 5 Clock Distribution
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
71