PE
PT
RE
VARIABLE 12-BIT RECEIVE
S
T
O
P
S
T
A
R
T
RECEIVE
WAKEUP
DATA BUFFER
INTERNAL BUS
MODULE
SBR12:0
BAUDRATE
CLOCK
RAF
LOGIC
SHIFT DIRECTION
ACTIVE EDGE
DETECT
BRFA4:0
SHIFT REGISTER
M
M10
RXINV
IRQ / DMA
LOGIC
DMA Requests
IRQ Requests
PARITY
LOGIC
CONTROL
RxD
RxD
LOOPS
RSRC
From Transmitter
RECEIVER
SOURCE
CONTROL
7816 LOGIC
To TxD
MSBF
GENERATOR
Figure 38-2. UART receiver block diagram
38.5.2.1 Receiver character length
The UART receiver can accommodate 8-, 9-, or 10-bit data characters. The states of
C1[M], C1[PE] and C4[M10] determine the length of data characters. When receiving 9
or 10-bit data, C3[R8] is the ninth bit (bit 8).
38.5.2.2 Receiver bit ordering
When S2[MSBF] is set, the receiver operates such that the first bit received after the start
bit is the MSB of the dataword. Similarly, the bit received immediately preceding the
parity bit, or the stop bit if parity is not enabled, is treated as the LSB for the dataword.
All necessary bit ordering is handled automatically by the module. Therefore, the format
of the data read from receive data buffer is completely independent of S2[MSBF].
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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