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27.2.3 MCG Status Register (MCG_S)
Address: 4006_4000h base + 6h offset = 4006_4006h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
1
0
0
MCG_S field descriptions
Field
Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–2
CLKST
Clock Mode Status
Indicates the current clock mode. This field does not update immediately after a write to MCG_C1[CLKS]
due to internal synchronization between clock domains.
00
HIRC clock is selected as the main clock source, and MCG_Lite works at HIRC mode.
01
LIRC clock is selected as the main clock source, and MCG_Lite works at LIRC2M or LIRC8M mode.
10
External clock is selected as the main clock source, and MCG_Lite works at EXT mode.
11
Reserved.
1
OSCINIT0
OSC Initialization Status
This flag, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock are
completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the Oscillator
(OSC) chapter for more information.
0
OSC is not ready.
1
OSC clock is ready.
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27.2.4 MCG Status and Control Register (MCG_SC)
Address: 4006_4000h base + 8h offset = 4006_4008h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
MCG_SC field descriptions
Field
Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
437