DMA_DARn field descriptions (continued)
Field
Description
• 0x000x_xxxx
• 0x1FFx_xxxx
• 0x200x_xxxx
• 0x400x_xxxx
After being written with one of the allowed values, bits 31-20 read back as the written value.
After being written with any other value, bits 31-20 read back as an indeterminate value.
21.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)
DSR and BCR are two logical registers that occupy one 32-bit address. DSRn occupies
bits 31–24, and BCRn occupies bits 23–0. DSRn contains flags indicating the channel
status, and BCRn contains the number of bytes yet to be transferred for a given block.
On the successful completion of the write transfer, BCRn decrements by 1, 2, or 4 for 8-
bit, 16-bit, or 32-bit accesses, respectively. BCRn is cleared if a 1 is written to
DSR[DONE].
In response to an event, the DMA controller writes to the appropriate DSRn bit. Only a
write to DSRn[DONE] results in action. DSRn[DONE] is set when the block transfer is
complete.
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 4 or 2 when
the DMA is configured for 32-bit or 16-bit transfers, respectively, DSRn[CE] is set and
no transfer occurs.
Address: 4000_8000h base + 108h (16d × i), where i=0d to 3d
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chapter 21 DMA Controller Module
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
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