42.3.1.1 Decorated store logical AND (AND)
This command performs an atomic read-modify-write of the referenced memory location.
1. First, the location is read;
2. It is then modified by performing a logical AND operation using the write data
operand sourced for the system bus cycle
3. Finally, the result of the AND operation is written back into the referenced memory
location.
The data size is specified by the write operation and can be byte (8-bit), halfword (16-bit)
or word (32-bit). The core performs the required write data lane replication on byte and
halfword transfers.
ioandb 0 *
0 0 1
mem_addr
ioandh 0
0 0 1
mem_addr
ioandw 0
0 0 1
mem_addr
*
*
*
*
*
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Figure 42-3. Decorated store address: logical AND
See
, where addr[30:29] = 10 for peripheral, addr[28:26] = 001 specifies the
AND operation, and mem_addr[19:0] specifies the address offset into the space based at
0x4000_0000 for peripherals. The "-" indicates an address bit "don't care".
The decorated AND write operation is defined in the following pseudo-code as:
ioand<sz>(accessAddress, wdata) // decorated store AND
tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read
tmp = tmp & wdata // modify
mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write
where the operand size <sz> is defined as b(yte, 8-bit), h(alfword, 16-bit) and w(ord, 32-
bit). This notation is used throughout the document.
In the cycle definition tables, the notations AHB_ap and AHB_dp refer to the address and
data phases of the BME AHB transaction. The cycle-by-cycle BME operations are
detailed in the following table.
Table 42-1. Cycle definitions of decorated store: logical AND
Pipeline stage
Cycle
x
x+1
x+2
BME AHB_ap
Forward addr to memory;
Decode decoration; Convert
Recirculate captured addr +
attr to memory as slave_wt
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Functional description
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
836
Freescale Semiconductor, Inc.
