TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual
13-40
V2.0, 2007-07
EBU, V2.0
modified bits in an external peripheral), the user’s software must ensure data coherency
through the use of the DLOAD bit(s).
When the EBU receives an external bus read access that represents a code fetch (i.e.
was generated by the PMU) to a memory region with “pre-fetch” enabled (via bit
PREFETCH in registers EBU_BUSCON or EBU_EMUBC), the EBU will perform a code
prefetch into the Code Prefetch Buffer.
13.6.2
Code Prefetch Buffer
This buffer consists of four 64-bit words (8
×
32-bit) which is enough to service a PLMB
four-word burst read request (BTR4). This four-word burst read is sufficient to load the
code cache line size of the TriCore CPU. When the code is highly sequential, the
prefetch buffer can help to speed up the instruction fetch process. This feature is
programmable through the PREFETCH bit in registers EBU_BUSCON or EBU_EMUBC.
On an instruction fetch cycle, a transaction originated from the PMU (most likely a cache
line refill) takes place on the PLMB. This transaction is handled via the Data Read Buffer.
At the end of the transaction, a prefetch activity is triggered to fill up the Code Prefetch
Buffer by reading the next four consecutive 64-bit words.
When using Burst Flash memories, the prefetch is performed by extending the access
by the appropriate number of cycles to fetch the next four 64-bit words. For
asynchronous memories, the prefetch is performed by generating the appropriate
number of device read accesses.
The result of the prefetch will be that the Code Prefetch Buffer will be ready with the
instructions when the next request for sequential instructions arrives.
The allows the cancellation of a pending prefetch if a new data access starts during the
code prefetch access. This feature is separately selectable for each chip select region,
and controlled by bit WEAKPREF in registers EBU_BUSCON or EBU_EMUBC.
Note: A code prefetch is only triggered by a PMU read access that is handled via the
Data Read Buffer. A PMU read access that is serviced by the Code Prefetch Buffer
will not generate a subsequent code prefetch.
13.6.3
Data Write Buffer
This buffer consists of four 64-bit words (8
×
32-bit). This is enough to service PLMB write
transactions up to and including a PLMB four-word burst write request (BTR4). This four-
word burst write is sufficient to support the date cache line size of the TriCore CPU.
When any PLMB-to-external-bus data write transaction occurs, this transaction will be
translated to the appropriate number of external bus write accesses. The Data Write
Buffer allows the EBU to accept data from the PLMB (from a single PLMB transaction)
faster than data can be written to the external bus, and also allows the EBU to complete
the PLMB request associated with one PLMB-to-external-bus data write transaction
while the external bus is busy (e.g. in the case of an ongoing code prefetch).
