TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual
12-27
V2.0, 2007-07
DMA, V2.0
12.1.8
Interrupts
The interrupt structure of the DMA controller is a very flexible control logic that allows an
interrupt coming from an interrupt source within four interrupt source types to be
connected to each of the sixteen interrupt outputs. This permits, for example, DMA
channels that generate interrupts very rarely to share one interrupt node. The remaining
interrupt nodes can be assigned to dedicated DMA channels to reduce the interrupt
overhead for these channels. The four interrupt source types are:
•
Channel interrupts
•
Transaction lost interrupt
•
Move Engine interrupts
•
Wrap buffer interrupts
Some of the interrupt functions are common to all of the four interrupt source types. An
interrupt event, internally generated as a request pulse, is always stored in an interrupt
status flag. This interrupt status flag can be cleared by software. Further, the interrupt
event can be enabled or disabled. When an interrupt event is enabled, a 4-bit Interrupt
Node Pointer determines which of the sixteen interrupt outputs will be activated.
The following sections describe each of the four interrupt source types in more detail.
12.1.8.1 Channel Interrupts
Each DMA channel mn has one associated channel interrupt. It can always be activated
after a DMA transfer, or when CHSRmn.TCOUNT matches with the value of bit field
CHSRmn.IRDV after it has been decremented after a DMA transfer. The pattern
detection interrupts that are combined with the channel interrupts (one common Interrupt
Node Pointer CHICRmn.INTP), are activated when the pattern detection interrupt of
DMA channel mn becomes active (when enabled by CHCRmn.PATSEL not equal 00
B
).
A channel interrupt of DMA channel mn is indicated when status flag INTSR.ICHmn is
set. The status flags ICHmn and IPMmn can be cleared together by software when
setting bit INTCR.CICHmn (or CHRSTR.CHmn). The channel interrupt of DMA channel
mn is enabled when bit CHICRmn.INTCT[1] is set. The channel interrupt pointer
CHICRmn.INTP determines which of the interrupt outputs SR[15:0]
1)
will be activated on
an active channel interrupt or pattern detection interrupt. Note that the signal that is the
set signal for the ICHmn flag is available as CHmn_OUT signal at the DMA module
boundary.
Bit CHICRmn.INTCT[0] selects two types of interrupt sources. For the compare
operation, bit field IRDV (4-bit) is zero-extended to 9-bit and then compared with the 9-bit
TCOUNT value. This means that a TCOUNT match interrupt can be generated after one
of the last 16 DMA transfers of a DMA transaction. Note that with IRDV = 0000
B
, the
1) In the TC1796, only SR[7:0] are connected to interrupt nodes.