Infineon Technologies TC1796, Руководство пользователя

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TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-128 V2.0, 2007-07
MLI, V2.0
23.5.3 Module Clock Generation
The module clock generation configuration for the two MLI modules is shown in
Figure 23-54 .
Figure 23-54 Clock Configuration of the MLI Modules
The two MLI modules (MLI0 and MLI1) are supplied from a common module clock
f
DMA
,
that has the frequency of the system clock
f
SYS
(=
f
FPI
) and is controlled via the
DMA_CLC clock control register. The MLI modules do not have its own clock control
registers. Its module clocks
f
MLI0
and
f
MLI1
are derived from
f
DMA
by two separate
fractional divider registers, MLI0_FDR and MLI1_FDR (FDR description see Page 23-79
and baud rate generation see Section 23.2.7 on Page 23-65 ).
Note: Additional details on the fractional divider register functionality are described in
section “Fractional Divider Operation” on Page 3-29 of the TC1796 User’s
Manual System Units part (Volume 1).
•
f
DMA
This is the module clock used inside the MLI kernels for control purposes such as for
clocking of control logic and register operations. The clock control register DMA_CLC
makes it possible to enable/disable
f
DMA
under certain conditions. DMA_CLC is
described in the DMA chapter of this document.
•
f
MLI0
and
f
MLI1
This clock is the module clock used in the MLI kernels as base for the shift clock and
therefore determines the baud rate of the synchronous serial data transmission. The
fractional divider registers MLI0_FDR and MLI1_FDR control the frequencies of
f
MLI0
and
f
MLI1
. This configuration makes it possible to enable/disable the module clocks
f
MLI0
and
f
MLI1
independently of
f
DMA
.
DMA Clock
Control
(DMA_CLC)
MCA05909_mod
f
ML I0
f
D MA
(=
f
C LC
)
MLI0
Module
Kernel
MLI1
Module
Kernel
MLI 0_FDR MLI 1_FDR
f
ML I1
f
SYS