Infineon Technologies TC1796, Руководство пользователя

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TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-63 V2.0, 2007-07
Ports, V2.0
10.9.3 Port 6 Registers
The following registers are available on Port 6:
Note: The complete address map of Port 6 is described in Table 18-15 on Page 18-28
of this TC1796 System Units (Vol. 1 of 2) User’s Manual.
10.9.3.1 Port 6 Output Register
The basic P6_OUT register functionality is described on Page 10-13 . Port lines P6.[3:0]
are not connected to port lines. Therefore, reading the P6_OUT bits P[3:0] returns the
value that was last written (0 after reset). These bits can be also set/cleared by the
corresponding P6_OMR bits.
10.9.3.2 Port 6 Output Modification Register
The basic P6_OMR register functionality is described on Page 10-14 . Port lines P6.[3:0]
are not available. Therefore, they are not implemented. These bits should always be
written with 0.
10.9.3.3 Port 6 Input Register
The basic P6_IN register functionality is described on Page 10-17 . Port lines P6.[3:0] are
not available. Therefore, the P6_IN bits P[3:0] are always read as 0.
Table 10-20 Port 6 Registers
Register
Short Name
Register Long Name Offset
Address Description
see
P6_OUT Port 6 Output Register 0000
H
below
1)
1) These registers are listed and noted here in the Port 6 section because they differ from the general port
register description given in Section 10.2 .
P6_OMR Port 6 Output Modification Register 0004
H
P6_IOCR4 Port 6 Input/Output Control Register 4 0014
H
Page 10-8
P6_IOCR8 Port 6 Input/Output Control Register 8 0018
H
Page 10-8
P6_IOCR12 Port 6 Input/Output Control Register 12 001C
H
Page 10-9
P6_IN Port 6 Input Register 0024
H
below
1)
P6_PDR Port 6 Pad Driver Mode Register 0040
H
Page 10-64
1)