TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual
20-25
V2.0, 2007-07
SSC, V2.1
A
Receive Error
(Master or Slave Mode) is detected when a new data frame is
completely received, but the previous data was not read out of the receive buffer register
RB. This condition sets the error flag STAT.RE and, if enabled via CON.REN, sets the
error interrupt request line EIR. The old data in the receive buffer RB will be overwritten
with the new value and is irretrievably lost.
A
Phase Error
(Master or Slave Mode) is detected when the incoming data at pin MRST
(Master Mode) or MTSR (Slave Mode), sampled with the same frequency as the module
clock, changes between one cycle before and two cycles after the latching edge of the
shift clock signal SCLK. This condition sets the error status flag STAT.PE and, if enabled
via CON.PEN, the error interrupt request line EIR.
Note: When CON.PH = 1, the data output signal may be disturbed shortly when the
slave select input signal is changed after a serial transmission, resulting in a phase
error.
A
Baud Rate Error
(Slave Mode) is detected when the incoming clock signal deviates
from the programmed baud rate (shift clock) by more than 100%, meaning it is either
more than double or less than half the expected baud rate. This condition sets the error
status flag STAT.BE and, if enabled via CON.BEN, the EIR line. Using this error
detection capability requires that the slave’s shift clock generator is programmed to the
same baud rate as the master device. This feature detects false additional pulses or
missing pulses on the clock line (within a certain frame).
Note: If this error condition occurs and bit CON.AREN = 1, an automatic reset of the
SSC will be performed. This is done to re-initialize the SSC, if too few or too many
clock pulses have been detected.
Note: This error can occur after any transfer if the communication is stopped. This is due
to the fact that SSC supports back-to-back transfers for multiple transfers. In order
to handle this, the baud rate detection logic expects a next clock cycle immediately
for a new transfer after a finished transfer.
If baud rate error is enabled and the transmit buffer of the slave SSC is loaded with a
new value for the next data frame while the current data frame is not yet finished, the
slave SSC expects continuation of the clock pulses for the next data frame transmission
immediately after finishing the current data frame. Therefore, if the master (shift) clock is
not continued, the slave SSC will detect a baud rate error. Note that the master SSC
does not necessarily send out a continuous shift clock in the case that it’s transmit buffer
is not yet filled with new data or transmission delays occur.
A
Transmit Error
(Slave Mode) is detected when a transfer was initiated by the master
(shift clock becomes active), but the transmit buffer TB of the slave was not updated
since the last transfer. This condition sets the error status flag STAT.TE and, if enabled
via CON.TEN, the EIR line. If a transfer starts while the transmit buffer is not updated,
the slave will shift out the ‘old’ contents of the shift register, which is normally the data
received during the last transfer. This may lead to the corruption of the data on the
