Infineon Technologies TC1796, Руководство пользователя

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TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-16 V2.0, 2007-07
FADC, V2.0
26.1.6.2 Filter Block Operation
Figure 26-8 illustrates how filter output values are calculated in a filter block. The
following conditions are set for this example:
•
A continuous A/D conversion is running on channel x.
• The filter input selection is set to channel x (FCRn.INSEL = 1XX
B
+ x).
• The addition length is 4 (FCRn.ADDL = 011
B
). This means that four conversion
results build one intermediate result.
• The final result is calculated by a moving average over the last four intermediate
results (FCRn.MAVL = 11
B
).
• The filter registers are at initial state (loaded with 0000
H
).
Figure 26-8 Filter Block Algorithm
0 0 0 0 0
MCT06045
CV
0
CV
1
CV
2
CV
3
CV
4
CV
5
CV
6
CV
7
CV
8
CV
9
CV
10
CV
11
CV
12
CV
13
CV
14
CV
15
CV
16
CV
17
CV
18
CV
19
CV
20
CV
21
CV
22
CV
23
Initial Start of
Filter Algorithm
Time
0
IRR1
0
IRR2
0
IRR3
IR1
0
0
IR2
IR1
0
IR3
IR2
IR1
0+0+0+0
FRR
0+0+0+IR1 0+0+IR1+IR2
C
0+IR1+IR2+IR3
C C C
IR1+IR2+IR3+IR4 IR2+IR3+IR4+IR5
0
CRR
CV
0
CV
0
+
CV
1
CV
0
+
CV
1
+C
V
2
CV
4
CV
4
+
CV
5
CV
4
+
CV
5
+C
V
6
CV
8
CV
8
+
CV
9
CV
8
+
CV
9
+C
V
1
0
CV
1
2
CV
1
2
+C
V
1
3
CV
1
2
+C
V
1
3
+C
V
1
4
IR4
IR3
IR2
CV
1
6
CV
1
6
+C
V
1
7
CV
1
6
+C
V
1
7
+C
V
1
8
IR5
IR4
IR3
CV
2
0
CV
2
0
+C
V
2
1
CV
2
0
+C
V
2
1
+C
V
2
2
C C
Time
0 0 0 0 0
C
1
0
2
3
1
0
2
3
1
0
2
3
1
0
2
3
1
0
2
3
1
0
2
3
AC
MAVS 0
Intermediate Result
Calculation
IRQFn
FRR = Content of the final result register.
IRR1-IRR3 = Content of the intermediate result registers.
CVy = Conversion results of one channel, numbered by y.
C = Calculation of intermediate and final results.
IRk = Intermediate results, numbered by k.
AC = Addition counter for current result.
MAVS = Moving average counter.
CRR = Content of current result register.
IRQFn = Interrupt flags CRSR.IRQFn set.