TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual
23-73
V2.0, 2007-07
MLI, V2.0
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The value of DELTA depends on the possible variations of the propagation
characteristics of the MLI connection. If the environment does not significantly
change, DELTA can be 1. For systems with variations, DELTA could be bigger. The
user can check about changing propagation characteristics by reading
TSTATR.RDC from time to time and to check if it is constant for correct transfers. If
it changes, either a bigger DELTA value can be applied, or the delay adjustment can
be repeated, adapting to the new circumstances.
23.3.6
Connection to DMA Mechanism
The MLI module supports the connection to a DMA (direct memory access) mechanism.
This mechanism allows the transfer of blocks of data of programmable size via an MLI
connection without CPU intervention. Therefore, a DMA mechanism can be used in the
Local Controller to write the desired number of data words one after the other to the
corresponding MLI Transfer Window. The address ranges of the data blocks and their
length has to be handled by the DMA module.
An MLI pipe supporting only one pending Write Frame request at a time, the DMA has
to wait until the pipe is capable to handle new data before writing another data word to
the Transfer Window. Therefore, the Normal Frame sent events of the pipes can trigger
DMA data transfers. Depending on the connection of the MLI module’s service request
outputs SRx to the DMA trigger inputs, the Normal Frame sent events have to be
enabled for service request activation and directed to the desired SRx outputs. It is
recommended to use only one type of MLI event per SRx output to trigger a data transfer
by DMA. If the DMA mechanism needs a start trigger for the first data word transfer,
register GINTR can be written with the appropriate pattern to activate an SRx output.
23.3.7
Connection of MLI to SPI
The handshake signals between a transmitter and a receiver are based on a
synchronous transfer protocol. In the SPI protocol, the shift clock and the data signal are
equivalent to CLK and DATA. In case of an 4-wire SPI, the slave select signal represents
the VALID signal (the leading and the trailing delay have to be set up accordingly).
Contrary to the MLI, in the SPI protocol, a complete control handshake is not defined, so
the READY signal does not exist in SPI modules. As a result, the SPI communication
does not check by hardware for correct data transfer, but has to handle this on an upper
software layer. If using an SPI module for communication with an MLI transmitter or an
MLI receiver, the READY signal has to be handled by software or the handshake has to
be given up. This can be done by connecting the TVALID signal of an MLI transmitter to
one of its own TREADY inputs with polarity inversion. Like this, the TREADY input
directly following the inverted TVALID signal, the parity error indication and the Non-
Acknowledge error detection are not possible.
Furthermore, in the MLI protocol, the frames may have a different width, depending on
their type and selected buffer size. The different numbers of data bits per frame have
