TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual
24-35
V2.0, 2007-07
GPTA, V2.0
24.2.2.5 Clock Distribution Unit (CDU)
The Clock Distribution Unit (CDU) provides all Local and Global Timer Cells with a clock
bus containing eight different clock output signals CLK[7:0] and a special LTC prescaler
clock LTCPRE. These nine clock signals are generated out of eleven clock input signals
coming from different clock sources (see
).
The prescalers divide the GPTA module clock
f
GPTA
by a programmable 2
n
factor. Factor
n is defined by bit fields DFA02, DFA04, DFA06 and DFA07 of control register CKBCTR.
A bit field value of 15 disables the related prescaler and selects alternate sources for
clock bus lines 2, 4, 6 and 7. For clock bus line CLK2, a bit field value of 14 selects an
alternate source.
For clock bus line CLK3, the 2-bit wide bit field DFA03 of control register CKBCTR
selects one of the four available clocks.
The LTC prescaler clock LTCPRE is generated by dividing the
f
GPTA
module clock by a
factor defined by the 3-bit wide bit field DFALTC of control register CKBCTR. Note that
the LTCPRE clock is not a part of the clock bus but a clock signal that is distributed
directly from the CDU to each LTC except LTC63.
