TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual
11-4
V2.0, 2007-07
PCP, V2.0
11.2.2
PCP Code Memory
The Code Memory (CMEM) of the PCP holds the channel programs, consisting of PCP
instructions. All instructions of the PCP are 16 bits long; thus, the PCP accesses its
CMEM in 16-bit (half-word) quantities. With the 16-bit Program Counter (PC) of the PCP,
a maximum of 64 K 16-bit instructions can be addressed. This results in a maximum size
of the PCP code memory of 128 Kbytes. The actual type (Flash, ROM, SRAM, etc.) and
size of the code memory is implementation-specific; see
for the
implemented type and size of the code memory in the TC1796.
The PCP CMEM is viewed from the FPI Bus as a 32-bit wide memory, that must be
accessed with 32-bit (word) accesses, and is addressed with byte addresses. Thus, care
has to be taken when calculating PCP instruction FPI addresses. See
details.
Note: The PCP has a “Harvard” architecture and therefore cannot directly access the
CMEM other than reading instructions from it. It is recommended that the PCP
should not access CMEM via the FPI Bus.
11.2.3
PCP Parameter RAM
The PCP Parameter RAM (PRAM) is the local holding place for each channel program’s
context, and for general data storage. It is also an area that the PCP and the host
processor or other FPI Bus masters can use to communicate and share data.
While a portion of the PRAM is always implicitly used for the Context Save Areas (CSAs)
of the channel programs, the remaining area can be used for channel-specific or general
data storage. A programmable 8-bit Data Pointer (DPTR), concatenated with a 6-bit
offset, is provided for arbitrary access to the PRAM. The effective address is a 14-bit
word address, allowing a PRAM size of up to 64 Kbytes. The actual type (SRAM, DRAM,
etc.) and size of the parameter RAM is implementation-specific; see
implemented size of the PRAM in this derivative.
Both the PCP and FPI Bus masters address the PRAM as 32-bit words. There is no
concept of half-word or byte accesses to PRAM. FPI Bus masters must, however, use
byte addresses in order to access the PRAM. As for the CMEM, care has to be taken
when calculating PRAM FPI addresses. See
for details.
11.2.4
FPI Bus Interface
The PCP can access all peripheral units on the FPI Bus and other resources through the
FPI Bus interface. The PCP can become an FPI Bus slave, so that other FPI Bus master
may access CMEM and PRAM and the control and status registers in the PCP.
The CMEM and PRAM blocks are visible to FPI Bus masters as a block of memory on
the FPI Bus. If an FPI Bus master accesses CMEM or PRAM concurrently with the PCP,
the external FPI Bus master is given precedence over the PCP to avoid deadlocks. The
PCP access is stalled for several cycles until the FPI Bus master has completed its
