Toshiba TMPR4925, Manual

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Chapter 3 Signals
3-12
3.2 Boot Configuration
The ADDR[19:0], UAE, SADDR10 and TDO signals can also function as configuration signals for
initially setting various functions upon booting the system. The states of the configuration signals
immediately after the RESET* or PON* signal is deasserted are read as initial values for the TX4925
internal registers. A High signal level sets a value of 1 and a Low signal level sets a value of 0. UAE,
SADDR10 and ADDR[17,16,10] are used for testing. Ensure that these pins will not set to 0.
All configuration signals are provided with internal pull-up resistors. To drive a signal Low, pull down the
corresponding pin on the board using an approx. 4.7 k
Ω
resistor. Driving a signal High does not require a
pull-down resistor. Any signals defined as Reserved should not be pulled down.
Table 3.2.1 lists the functions that can be set using configuration signals. Table 3.2.2 and 3.2.3 describe
each configuration signal. Note that the functions of some pins vary with the boot memory device used.
Table 3.2.1 Functions that Can be Set Using Configuration Signals
Peripheral
Function
Functions that Can be Set
Configuration
Signal
PCICLK enable ADDR[18]
PCI controller operating mode (satellite or host) ADDR[15]
PCI bus arbiter selection (internal or external) ADDR[1]
PCI controller
PCI bus master
*
1
ADDR[11]
Division ratio of SYSCLK to GBUSCLK ADDR[4:3]
Boot device selection ADDR[8:6]
BE[3:0]
*
/BWE[3:0]
*
function selection upon booting ADDR[11]
Handling of the ACK signal upon booting (internal or external) ADDR[5]
External bus
controller
Data bus width for the boot device ADDR[13:12]
Endian setting ADDR[14]
Others Controlling built-in timer interrupts of the TX49/H2 core ADDR[0]
PC trace TDO
*
1: Valid when the boot memory device is PCI and the PCIC operates in satellite mode.