Toshiba TMPR4925, Manual

Page: 570 / 590

Chapter 22 Electrical Characteristics
22-6
22.5.4 External Bus Interface AC Characteristics
(Tc = 0 ~ 70
°
C, V
CCIO
= 3.3 V
±
0.3 V, V
CCInt
= 1.5 V
±
0.1 V, V
SS
= 0 V)
Parameter Symbol Rating Min. Max. Unit
SYSCLK Cycle Time t
CYC_SYSCLK
12.5
⎯
ns
SYSCLK HighTime t
HIGH_SYSCLK
4
⎯
ns
SYSCLK LowTime t
LOW_SYSCLK
4
⎯
ns
ADDR[19:5] Output delay t
VAL_ADDR2
1.5 9.5 ns
CE[5:0]
*
Output delay t
VAL_CE
1.5 9.0 ns
OE
*
Output delay t
VAL_OE
1.5 9.0 ns
SWE
*
Output delay t
VAL_SWE
1.5 9.0 ns
BWE[3:0]
*
Output delay t
VAL_BWE
1.5 9.0 ns
UAE Output delay t
VAL_UAE
1.5 9.0 ns
BUSSPRT * Output delay t
VAL_DQM
1.5 9.0 ns
DATA[31:0] Output delay (H
->
L, L
->
H) t
VAL_BUS
1.5 9.0 ns
DATA[31:0] Output delay (High-Z
->
Valid) t
VAL_DATA2ZV
1.5 9.0 ns
DATA[31:0] Output delay (Valid
->
High-Z) t
VAL_DATA2VZ
1.5 9.0 ns
DATA[31:0] Input set-up time t
SU_DATA2
6.0
⎯
ns
DATA[31:0] Input set-up time t
HO_DATA2
1.0
⎯
ns
ACK * Output delay (H
->
L, L
->
H) t
VAL_ACK
1.5 9.0 ns
ACK * Output delay (High-Z
->
Valid) t
VAL_ACKZV
1.5 9.0 ns
ACK * Output delay (Valid
->
High-Z) t
VAL_ACKVZ
1.5 9.0 ns
ACK * Input set-up time t
SU_ACK
6.0
⎯
ns
ACK * I nput hold time t
HO_ACK
0.5
⎯
ns
Figure 22.5.5 Timing Diagrams: External Bus Interface
SYSCLK
OUTPUT
INPUT
t
SU_
*
t
HO_
*
t
HIGH_SYSCLK
t
LOW_SYSCLK
outputs valid
inputs valid
t
VAL_ *
t
CYC_SYSCLK