Chapter 10 PCI Controller
10-43
10.4.16 Satellite Mode PCI Status Register (PCISSTATUS)
0xD088
The PCI Status, Command Register (PCISTATUS) or the PMCSR Register of the Configuration
Space cannot be accessed when the PCI Controller is in the Satellite mode. It is possible however to
read values from either of these registers.
Note: Read this field in the following procedures. If other procedures are used, incorrect data
may be read.
(1) General
procedures
After checking the P2GSTATUS.PMSC bit is set, read the PS field.
(2) Procedures to read at any time
To read PS field directly, but not using the procedures shown above (1), read the PS field
twice consecutively. Use the value if the same value is read.
31
26
25
24
23
16
Reserved PS
Reserved
R
: Type
00
: Initial value
15
14
13
12
11
10
9
8
7 0
DPE SSE RMA RTA STA
DT
MDPE
Reserved
R
R
R
R
R
R
R
:
Type
0
0
0
0
0
01
0
:
Initial
value
Bits Mnemonic Field
Name
Description
31:26
⎯
Reserved
⎯
25:24
PS
Power State
PowerState (Initial value: 00, R)
This is a shadow register of the PowerState field in the PMCSR Register.
Note: Read this field in the following procedures. If other procedures are used,
incorrect data may be read.
(1) General procedures
After checking the P2GSTATUS.PMSC bit is set, read the PS field.
(2) Procedures to read at any time
To read PS field directly, but not using the procedures shown above (1), read the
PS field twice consecutively. Use the value if the same value is read.
23:16
⎯
Reserved
⎯
15 DPE
Detected Parity
Error
Detected Parity Error (Initial value: 0, R)
This is a shadow register of the PCISTATUS.DPE bit.
14 SSE
Signaled System
Error
Signaled System Error (Initial value: 0, R)
This is a shadow register of the PCISTATUS.SSE bit.
13 RMA
Received Master
Abort
Received Master Abort (Initial value: 0, R)
This is a shadow register of the PCISTATUS.RMA bit.
12 RTA
Received Target
Abort
Received Target Abort (Initial value: 0, R)
This is a shadow register of the PCISTATUS.RTA bit.
11 STA
Signaled Target
Abort
Signaled Target Abort (Initial value: 0, R)
This is a shadow register of the PCISTATUS.STA bit.
10:9 DT
Set DEVSEL
Timing
DEVSEL Timing (Fixed value: 01, R)
This is a shadow register of the PCISTATUS.DT field.
8 MDPE
Data
Parity
Detected
Master Data Parity Error Detected (Initial value: 0, R)
This is a shadow register of the PCISTATUS.MDPE bit.
7:0
⎯
Reserved
⎯
Figure 10.4.16 Satellite Mode PCI Status Register
Summary of Contents for TMPR4925
Page 1: ...64 Bit TX System RISC TX49 Family TMPR4925 Rev 3 0 ...
Page 4: ......
Page 15: ...Handling Precautions ...
Page 16: ......
Page 18: ...1 Using Toshiba Semiconductors Safely 1 2 ...
Page 40: ...3 General Safety Precautions and Usage Considerations 3 18 ...
Page 42: ...4 Precautions and Usage Considerations 4 2 ...
Page 43: ...TMPR4925 ...
Page 44: ......
Page 54: ...Chapter 1 Features 1 8 ...
Page 58: ...Chapter 2 Block Diagram 2 4 ...
Page 88: ...Chapter 4 Address Mapping 4 12 ...
Page 226: ...Chapter 8 DMA Controller 8 58 ...
Page 260: ...Chapter 9 SDRAM Controller 9 34 ...
Page 480: ...Chapter 15 Interrupt Controller 15 32 ...
Page 554: ...Chapter 19 Real Time Clock RTC 19 8 ...
Page 555: ...Chapter 20 Removed 20 1 20 Removed ...
Page 556: ...Chapter 20 Removed 20 2 ...
Page 564: ...Chapter 21 Extended EJTAG Interface 21 8 ...
Page 580: ...Chapter 22 Electrical Characteristics 22 16 ...
Page 588: ...Chapter 24 Usage Notes 24 2 ...