Toshiba TMPR4925, Manual

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Table of Contents
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Table of Contents
Handling Precautions
TX4925
1. Features................................................................................................................................................................... 1-1
1.1 Outline ........................................................................................................................................................... 1-1
1.2 Features .......................................................................................................................................................... 1-2
1.2.1 TX49/H2 Processor Core Features ........................................................................................................ 1-2
1.2.2 TX4925 Peripheral Circuit Features...................................................................................................... 1-3
2. Block Diagram........................................................................................................................................................ 2-1
2.1 TX4925 Block Diagram................................................................................................................................. 2-1
3. Signals .................................................................................................................................................................... 3-1
3.1 Pin Signal Description ................................................................................................................................... 3-1
3.1.1 Signals Common to SDRAM and External Bus Interfaces ................................................................... 3-1
3.1.2 SDRAM Interface Signals..................................................................................................................... 3-2
3.1.3 External Interface Signals ..................................................................................................................... 3-3
3.1.4 DMA Interface Signals.......................................................................................................................... 3-5
3.1.5 PCI Interface Signals............................................................................................................................. 3-5
3.1.6 Serial I/O Interface Signals ................................................................................................................... 3-7
3.1.7 Timer Interface Signals ......................................................................................................................... 3-7
3.1.8 Parallel I/O Interface Signals ................................................................................................................ 3-7
3.1.9 AC-link Interface Signals...................................................................................................................... 3-8
3.1.10 Interrupt Signals .................................................................................................................................... 3-8
3.1.11 CHI Interface Signals ............................................................................................................................ 3-8
3.1.12 SPI Interface Signals ............................................................................................................................. 3-9
3.1.13 NAND Flash Memory Interface Signals ............................................................................................... 3-9
3.1.14 Extended EJTAG Interface Signals ....................................................................................................... 3-9
3.1.15 Clock Signals ...................................................................................................................................... 3-10
3.1.16 Initialization Signals............................................................................................................................ 3-10
3.1.17 Test Signals ......................................................................................................................................... 3-11
3.1.18 Power Supply Pins .............................................................................................................................. 3-11
3.2 Boot Configuration ...................................................................................................................................... 3-12
3.3 Pin Multiplexing .......................................................................................................................................... 3-15
4. Address Mapping.................................................................................................................................................... 4-1
4.1 TX4925 Physical Address Map...................................................................................................................... 4-1
4.2 Register Map.................................................................................................................................................. 4-2
4.2.1 Addressing............................................................................................................................................. 4-2
4.2.2 Ways to Access to Internal Registers..................................................................................................... 4-2
4.2.3 Register Map ......................................................................................................................................... 4-3
5. Configuration Register............................................................................................................................................ 5-1
5.1 Outline ........................................................................................................................................................... 5-1
5.1.1 Detecting G-Bus Timeout...................................................................................................................... 5-1
5.2 Register .......................................................................................................................................................... 5-2
5.2.1 Chip Configuration Register (CCFG) 0xE000 ..................................................................................... 5-3
5.2.2 Chip Revision ID Register (REVID) 0xE004 ....................................................................................... 5-5
5.2.3 Pin Configuration Register (PCFG) 0xE008 ........................................................................................ 5-6
5.2.4 Timeout Error Access Address Register (TOEA) 0xE00C................................................................... 5-8
5.2.5 Power Down Control Register (PDNCTR) 0xE010............................................................................. 5-9
5.2.6 GBUS Arbiter Priority Register (GARBP) 0xE018 ............................................................................ 5-10
5.2.7 Timeout Count Register (TOCNT) 0xE020 ....................................................................................... 5-10
5.2.8 DMA Request Control Register (DRQCTR) 0xE024 ........................................................................ 5-11
5.2.9 Clock Control Register (CLKCTR) 0xE028 ...................................................................................... 5-12
5.2.10 GBUS Arbiter Control Register (GARBC) 0xE02C ........................................................................... 5-14