Toshiba TMPR4925, Manual

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Chapter 10 PCI Controller
10-11
When expressed as a formula, conversion of a PCI Bus Address (PCIAddr[31:0]) into a G-Bus
address (GBusAddr[31:0]) is as follows below. GBASE[31:8], PBASE[31:8], and
AM[28:20]/AM[15:8] each represent the setting register of the corresponding access window indicated
below in Table 10.3.4. The “&” symbol indicates a logical AND for each bit, and “|” indicates bit
linking.
Memory space 0
If (PCIAddr[31:29] | ( PCIAddr[28:20] & !AM[28:20] ) == PBASE[31:29] |
( PBASE[28:20] & !AM[28:20])) then
GBusAddr[31:0] = GBASE[31:29] | ((GBASE[28:20] & !AM[28:20]) ||
(PCIAddr[28:20] & AM[28:20])) | PCIAddr[19:0];
Memory space 1
If (PCIAddr[31:29] | ( PCIAddr[28:20] & !AM[28:20] ) == PBASE[31:29] |
( PBASE[28:20] & !AM[28:20])) then
GBusAddr[31:0] = GBASE[31:29] | ((GBASE[28:20] & !AM[28:20]) ||
(PCIAddr[28:20] & AM[28:20])) | PCIAddr[19:0];
Memory space 2
If (PCIAddr[31:29] | ( PCIAddr[28:20] & !AM[28:20] ) == PBASE[31:29] |
( PBASE[28:20] & !AM[28:20])) then
GBusAddr[31:0] = GBASE[31:29] | ((GBASE[28:20] & !AM[28:20]) ||
(PCIAddr[28:20] & AM[28:20])) | PCIAddr[19:0];
I/O space
If (PCIAddr[31:8] == P2GIOPBASE.BA[31:8]) then
GBusAddr[31:0] = P2GIOGBASE[31:8] | PCIAddr[7:0];
Table 10.3.4 Target Access Space Address Mapping Register
PCI Bus Base Address
PBASE
G-Bus Base Address
GBASE
Address Mask
AM
Memory Space 0 P2GM0PLBASE.BA[31:20] P2GM0GBASE.BA[31:20] P2GM0CTR.AM[28:20]
Memory Space 1 P2GM1PLBASE.BA[31:20] P2GM1GBASE.BA[31:20] P2GM1CTR.AM[28:20]
Memory Space 2 P2GM2PBASE.BA[31:20] P2GM2GBASE.BA[31:20] P2GM2CTR.AM[28:20]
I/O Space P2GIOPBASE.BA[31:8] P2GIOGBASE.BA[31:8] P2GIOCTR.AM[15:8]