Toshiba TMPR4925, Manual

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Chapter 8 DMA Controller
8-17
The sequence of Chain DMA transfer is as follows below.
(1) Select DMA request signal
To perform external I/O or internal I/O DMA, set the DMA Request Select field of the DMA
Request Control Register (DRQCTR. DMAREQ). For external I/O DMA, also program the
function of the shared pin through the DMA Select field of the Pin Configuration Register
(PCFG.SELDMA).
(2) Set the Master Enable bit
Set the Master Enable bit (DMMCR.MSTEN) of the DMA Master Control Register.
(3) Structure of the DMA command Descriptor chain
Construct the DMA Command Descriptor Chain in memory.
(4) Set the Count Register
Set “0” to the DMA Count Register (DMCNTRn) .
Sets the DMA Source Address Increment Register (DMSAIRn) and DMA destination Address
Increment Register (MMDAIRn).
Never set 0 or less than 0 for the increment value.
(5) Clear the DMA Channel Status Register (DMCSRn)
Clear the status of the previous DMA transfer.
(6) Set the DMA Channel Control Register (DMCCRn).
(7) Initiate DMA transfer
Setting the address of the DMA Command Descriptor at the beginning of the chain list in the DMA
Chain Address Register (DMCHARn) automatically initiates DMA transfer. First, the value stored
in each field of the DMA Command descriptor at the beginning of the Chain List is read to each
corresponding DMA Channel register (Chain transfer), then DMA transfer is performed according
to the read value.
When a value other than “0” is stored in the DMA Chain Address Register (DMCHARn), data of
the size stored in the DMA Count Register (DMCNTRn) is completely transferred, then the DMA
Command Descriptor value of the memory address specified by the DMA Chain Address Register
is read.
In addition, if the Chain Address field value read the Descriptor 0, the DMA Chain Address
Register value is not updated. All previous values (Data Command Descriptor Addresses with the
value “0” in the Chain Address field when the values were read) are held.